參數(shù)資料
型號： ADV7312
廠商： Analog Devices, Inc.
英文描述： Multiformat 11-Bit HDTV Video Encoder
中文描述： 多格式11位高清晰度電視視頻編碼器
文件頁數(shù)： 30/84頁
文件大小： 975K
代理商： ADV7312
REV. 0
–30–
ADV7312
INPUT CONFIGURATION
Note that the ADV7312 defaults to simultaneous standard
definition and progressive scan on power-up.
Address[01h] : Input Mode = 011
Standard Definition Only
Address[01h] : Input Mode = 000
The 8-bit multiplexed input data is input on Pins S7–S0 (or
Y7–Y0, depending on Register Address 01h, Bit 7), with S0 being
the LSB in 8-bit input mode. Input standards supported are
ITU-R BT.601/656. In 16-bit input mode, the Y pixel data is
input on Pins S7–S2 and CrCb data on Pins Y7–Y0.
16-Bit Mode Operation
With Reg 01h Bit 7 = 0
CrCb data is input on Y Bus
Y data is input on S Bus
With Reg 01h Bit 7 = 1
CrCb data is input on C Bus
Y data is input on Y Bus
The 27 MHz clock input must be input on Pin CLKIN_A.
Input sync signals are optional and are input on the S_VSYNC,
S_HSYNC, and S_BLANK pins.
MPEG2
DECODER
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S[7:0] OR Y[7:0]
*
27MHz
3
8
YCrCb
ADV7312
*
SELECTED BY ADDRESS 0x01 BIT 7
Figure 21. SD Only Input Mode
Progressive Scan Only or HDTV Only
Address[01h] Input Mode 001 or 010, Respectively
YCrCb progressive scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data
is input on Pins Y7–Y0 and the CrCb data on Pins C7–C0. In
4:4:4 input mode, Y data is input on Pins Y7–Y0, Cb data on
Pins C7–C0, and Cr data on Pins S7–S0. If the YCrCb data
does not conform to SMPTE 293M (525p), ITU-R BT.1358M
(625p), SMPTE 274M[1080i], SMPTE 296M[720p], or
BTA-T1004/1362, the async timing mode must be used. RGB
data can only be input in 4:4:4 format in PS input mode only or
HDTV input mode only when HD RGB input is enabled. G data
is input on Pins Y7–Y0, R data on S7–S0, and B data on C7–C0.
The clock signal must be input on Pin CLKIN_A.
MPEG2
DECODER
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
C[7:0]
8
Cb
S[7:0]
Y[7:0]
INTERLACED TO
PROGRESSIVE
YCrCb
8
Cr
8
Y
3
27MHz
ADV7312
Figure 22. Progressive Scan Input Mode
Simultaneous Standard Definition and
Progressive Scan or HDTV
Address[01h] : Input Mode 011(SD 8-Bit, PS 16-Bit) or
101(SD and HD, SD Oversampled), 110(SD and HD, HD
Oversampled), Respectively
YCrCb, PS, HDTV, or any other HD data must be input in
4:2:2 format. In 4:2:2 input mode the HD Y data is input on
Pins Y7–Y0 and the HD CrCb data on C7–C0. If PS 4:2:2 data
is interleaved onto a single 8-bit bus, Y7–Y0 are used for the
input port. The input data is to be input at 27 MHz, with the
data being clocked on the rising and falling edge of the input
clock. The input mode register at Address 01h is set accord-
ingly. If the YCrCb data does not conform to SMPTE 293M
(525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i],
SMPTE 296M[720p], or BTA-T1004, the async timing mode
must be used.
The 8-bit standard definition data must be compliant with
ITU-R BT.601/656 in 4:2:2 format. Standard definition data is
input on Pins S7–S0, with S0 being the LSB. Using 8-bit input
format, the data is input on Pins S7–S2. The clock input for SD
must be input on CLKIN_A and the clock input for HD must
be input on CLKIN_B. Synchronization signals are optional. SD
syncs are input on Pins
S_VSYNC
,
S_HSYNC
, and
S_BLANK
.
HD syncs on Pins
P_VSYNC
,
P_HSYNC
, and
P_BLANK
.
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
MPEG2
DECODER
3
27MHz
8
YCrCb
INTERLACED TO
PROGRESSIVE
8
CrCb
8
Y
3
27MHz
S[7:0]
C[7:0]
Y[7:0]
ADV7312
Figure 23. Simultaneous PS and SD Input
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
SDTV
DECODER
3
27MHz
8
YCrCb
8
CrCb
8
Y
3
74.25MHz
1080i
OR
720p
S[7:0]
C[7:0]
Y[7:0]
ADV7312
HDTV
DECODER
Figure 24. Simultaneous HD and SD Input
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