參數(shù)資料
型號： ADV7303A
廠商： Analog Devices, Inc.
英文描述： Sand Paper; Abrasive Grade:A VFN; Color:Maroon; Pack Quantity:4; Roll Length:30ft; Width:3"
中文描述： 多格式統(tǒng)計，逐行掃描/ HDTV視頻編碼器與六11位DAC
文件頁數(shù)： 29/68頁
文件大小： 1177K
代理商： ADV7303A
REV. A
ADV7302A/ADV7303A
–29–
INPUT AND OUTPUT CONFIGURATION
STANDARD DEFINITION ONLY
The 8-bit multiplexed input data is input on Pins S7–S0, with S0
being the LSB. ITU-R.BT601/ITU-R.BT656 input standards
are supported. In 16-bit Input Mode, the Y pixel data is input on
Pins S7–S0 and CrCb data on Pins Y7–Y0. The 27 MHz clock
input must be input on Pin CLKIN_A. Input sync signals are
optional and are input on the
S_VSYNC
,
S_HSYNC
, and
S_BLANK
pins.
MPEG2
DECODER
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S7–S0
27MHz
3
8
YCrCb
ADV7302A/
ADV7303A
Figure 20. Standard Definition Only Input Mode
PROGRESSIVE SCAN ONLY OR HDTV ONLY
YCrCb Progressive Scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4 format. In 4:2:2 Input Mode, the
Y data is input on Pins Y7–Y0 and the CrCb data on Pins C7–
C0. In 4:4:4 Input Mode, Y data is input on Pins Y7–Y0, Cb
data on Pins C7–C0, and Cr data on Pins S7–S0. If the
YCrCb data does not conform to SMPTE293M (525 p),
ITU-R.BT1358M (625 p), SMPTE274M (1080 i),
SMPTE296M (720 p), or BTA-T1004, the Async Timing Mode
must be used. RGB data can only be input in 4:4:4 format in
PS Input Mode only, or HDTV Input Mode only, when HD
RGB input is enabled. G data is input on Pins Y7–Y0, R data
on S7–S0, and B data on Pins C7–C0. The clock signal must
be input on Pin CLKIN_A. Synchronization signals are optional
and are input on Pins
P_VSYNC
,
P_HSYNC
, and P_BLANK.
MPEG2
DECODER
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
S7–S0
8
Cr
C7–C0
Y7–Y0
INTERLACED
TO
PROGRESSIVE
YCrCb
8
Cb
8
Y
3
27MHz
ADV7302A/
ADV7303A
Figure 21. Progressive Scan Only Input Mode
SIMULTANEOUS STANDARD DEFINITION AND
PROGRESSIVE SCAN OR HDTV
YCrCb PS, HDTV, or any other HD data must be input in 4:2:2
format. In 4:2:2 Input Mode, the Y data is input on Pins Y7–Y0
and the CrCb data on C7–C0. If PS 4:2:2 data is interleaved onto a
single 8-bit bus, Pins Y7–Y0 are used for the input port. The inter-
leaved data is to be input at 27 MHz in setting the Input Mode
Register at Address 01h accordingly. If the YCrCb data does not
conform to SMPTE293M (525 p), ITU-R.BT1358M (625 p),
SMPTE274M (1080 i), SMPTE296M (720 p), or BTA-T1004,
the Async Timing Mode must be used.
The 8-bit standard definition data must be compliant to ITU-
R.BT601/ITU-R.BT656 in 4:2:2 format. Standard definition data
is input on Pins S7–S0, with S0 being the LSB. The clock input for
SD must be input on CLKIN_A, and the clock input for HD must
be input on CLKIN_B. Synchronization signals are optional. SD
syncs are input on Pins
S_VSYNC
,
S_HSYNC
, and
S_BLANK
; the HD syncs on Pins
P_VSYNC
,
P_HSYNC
, and
P_BLANK.
MPEG2
DECODER
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
C7–C0
8
CrCb
Y7–Y0
INTERLACED
TO
PROGRESSIVE
YCrCb
8
Y
3
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
3
27MHz
S7–S0
8
27MHz
ADV7302A/
ADV7303A
Figure 22. Simultaneous Progressive Scan and SD Input
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
SDTV
DECODER
3
27MHz
8
YCrCb
HDTV
DECODER
8
CrCb
8
Y
3
74MHz
1080 i
720 p
ADV7302A/
ADV7303A
S7–S0
C7–C0
Y7–Y0
Figure 23. Simultaneous HDTV and SD Input
If in Simultaneous Input Mode the two clock phases differ by less
than 9.25 ns or more than 27.75 ns, the Clock Align Bit must be
set accordingly. This also applies if the Pixel Align Bit is set. If
the application uses the same clock source for both SD and PS,
the Clock Align Bit must be set since the phase difference
between both inputs is less than 9.25 ns.
t
DELAY
t
DELAY
9.25ns OR
27.75ns
Figure 24. Clock Phase with Two Input Clocks
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