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參數(shù)資料
| 型號(hào)： | ADV7197KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Multiformat HDTV Encoder with Three 11-Bit DACs |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大?。?/td> | 229K |
| 代理商： | ADV7197KST |
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REV. 0
ADV7197
–10–
FUNCTIONAL DESCRIPTION
Digital Inputs
The digital inputs of the ADV7197 are TTL-compatible. 30-bit
YCrCb or RGB pixel data in 4:4:4 format or 20-bit YCrCb pixel
data in 4:2:2 format is latched into the device on the rising edge
of each clock cycle at 74.25 MHz or 74.1758 in HDTV mode.
It is recommended to input data in 4:2:2 mode to make use of
the Chroma SSAFs on the ADV7197. As can be seen in the
figures below, these filters have 0 dB passband response and
prevent signal components being folded back into the frequency
band. In 4:4:4 input mode, the video data is already interpo-
lated by an external input device and the chroma SSAFs of the
ADV7197 are bypassed.
RBW 10kHz
VBW 300Hz
SWP 17.0SEC
START 100kHz
STOP
20.00MHz
RL
–
10.0dBm
10dB/
3.18MHz
ATTEN
10dB
VAVG
1
MKR
0dB
Figure 6. SSAF Response to a 2.5 MHz Chroma Sweep
Using 4:2:2 Input Mode
RBW 10kHz
VBW
300Hz
SWP
17.0SEC
START
100kHz
STOP
20.00MHz
RL
–
10.0dBm
10dB/
3.12MHz
ATTEN
10dB
VAVG
4
MKR
–
3.00dB
Figure 7. Conventional Filter Response to a 2.5 MHz Chroma
Sweep Using 4:4:4 Input Mode
Control Signals
The ADV7197 accepts sync control signals accompanied by
valid 4:2:2 or 4:4:4 data. These external horizontal, vertical and
blanking pulses (or EAV/SAV codes) control the insertion of
appropriate sync information into the output signals.
Analog Outputs
The analog Y signal is output on the 11-bit + Sync DAC A,
the color component analog signals on the 11-bit DACs B, C
conforming to EIA-770.3 standards R
SET
has a value of 2470
(EIA-770.3), R
LOAD
has a value of 300
. For the outputs to con-
form to RS-170/RS-343A standards R
SET
must have a value
of 2820
.
Internal Test Pattern Generator
The ADV7197 can generate a Cross-Hatch pattern (white lines
against a black background). Additionally, the ADV7197 can
output a uniform color pattern. The color of the lines or uni-
form field/frame can be programmed by the user.
Y/CrCb Delay
The Y output and the color component outputs can be delayed
wrt the falling edge of the horizontal sync signal by up to four
clock cycles.
I
2
C Filter
A selectable internal I
2
C filter allows significant noise reduction
on the I
2
C interface. For setting ALSB high, the input band-
width on the I
2
C lines is reduced and pulses of less than 50 ns
are not passed to the I
2
C controller. Setting ALSB low allows
greater input bandwidth on the I
2
C lines.
MPU PORT DESCRIPTION
The ADV7197 support a 2-wire serial (I
2
C-compatible) micro-
processor bus driving multiple peripherals. Two inputs Serial
Data (SDA) and Serial Clock (SCL) carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7197 has four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 8. The LSB
sets either a read or write operation. Logic Level “1” corresponds
to a read operation while Logic Level “0” corresponds to a write
operation. A1 is set by setting the ALSB pin of the ADV7197 to
Logic Level “0” or Logic Level “1.” When ALSB is set to “0,”
there is greater input bandwidth on the I
2
C lines, which allows
high-speed data transfers on this bus. When ALSB is set to “1,”
there is reduced input bandwidth on the I
2
C lines, which means
that pulses of less than 50 ns will not pass into the I
2
C internal
controller. This mode is recommended for noisy systems.
0
X
1
0
1
0
1
A1
READ/WRITE
CONTROL
0
1
WRITE
READ
ADDRESS
CONTROL
SET UP BY
ALSB
Figure 8. Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transi-
tion on SDA while SCL remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
Start condition and shift the next eight bits (7-bit address + R/
W
bit). The bits are transferred from MSB down to LSB. The periph-
eral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known
as an Acknowledge Bit. All other devices withdraw from the bus
at this point and maintain an idle condition. The idle condition
is where the device monitors the SDA and SCL lines waiting for
the Start condition and the correct transmitted address. The R/
W
bit determines the direction of the data.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7197KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT HDTV ENCODER, 3 11-BIT DACS - Bulk |
| ADV7202 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Simultaneous Sampling Video Rate Codec |
| ADV7202KST | 制造商:Rochester Electronics LLC 功能描述:27MHZ DTV PICTURE IN PICTURE CODEC I.C. - Bulk 制造商:Analog Devices 功能描述: |
| ADV7202KSTZ | 功能描述:IC CODEC VIDEO 10BIT 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADV7280ABCPZ-M | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻 數(shù)據(jù)接口:I2C，串行 分辨率（位）:10 b ADC/DAC 數(shù):1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動(dòng)態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
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