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參數(shù)資料
| 型號： | ADV7197 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat HDTV Encoder with Three 11-Bit DACs |
| 中文描述： | 多格式HDTV編碼器三種11位DAC |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 229K |
| 代理商： | ADV7197 |
REV. 0
ADV7197
–14–
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Figure 17 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
With these bits it is possible to delay the Y signal with respect to
the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 16 demonstrates this facility.
Color Delay (MR23–MR25)
With theses bits it is possible to delay the color signals with
respect to the falling edge of the horizontal sync signal by up to
four pixel clock cycles. Figure 16 demonstrates this facility.
Reserved (MR26–MR27)
A “0” must be written to these bits.
MAX DELAY
NO DELAY
NO DELAY
MAX DELAY
PrPb DELAY
Y DELAY
Y OUTPUT
PrPb OUTPUTS
Figure 16. Y and Color Delay
MR21
MR27
MR22
MR24
MR25
MR23
MR20
MR26
MR25
0
0
0
0
1
MR24
0
0
1
1
0
MR23
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
COLOR DELAY
MR22
0
0
0
0
1
MR21
0
0
1
1
0
MR20
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
Y DELAY
ZERO MUST
BE WRITTEN
TO THESE BITS
MR27
–
MR26
Figure 17. Mode Register 2
MR37
MR32
MR34
MR36
ZERO MUST BE
WRITTEN TO
THESE BITS
MR37
–
MR36
MR34
0
1
POWER-DOWN
NORMAL
DAC B CONTROL
MR35
MR35
0
1
POWER-DOWN
NORMAL
DAC C CONTROL
MR33
MR31
MR30
MR33
0
1
POWER-DOWN
NORMAL
DAC A CONTROL
ZERO MUST BE
WRITTEN TO
THESE BITS
MR32
–
MR30
Figure 18. Mode Register 3
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)
Figure 18 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Reserved (MR31–MR32)
A “0” must be written to these bits.
DAC A Control (MR33)
Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
DAC B Control (MR34)
Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.
DAC C Control (MR35)
Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
Reserved (MR36–MR37)
A “0” must be written to these bits.
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PDF描述 |
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| ADV7197KST | Multiformat HDTV Encoder with Three 11-Bit DACs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7197KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT HDTV ENCODER, 3 11-BIT DACS - Bulk |
| ADV7197KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat HDTV Encoder with Three 11-Bit DACs |
| ADV7197KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT HDTV ENCODER, 3 11-BIT DACS - Bulk |
| ADV7202 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Simultaneous Sampling Video Rate Codec |
| ADV7202KST | 制造商:Rochester Electronics LLC 功能描述:27MHZ DTV PICTURE IN PICTURE CODEC I.C. - Bulk 制造商:Analog Devices 功能描述: |
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