參數(shù)資料
型號: ADV7196AKS
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP52
封裝: PLASTIC, MQFP-52
文件頁數(shù): 17/36頁
文件大?。?/td> 501K
代理商: ADV7196AKS
REV. 0
ADV7196A
–17–
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Figure 22 shows the various operations under the control of Mode
Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
This control bit delays the Y signal with respect to the falling edge
of the horizontal sync signal by up to four pixel clock cycles.
Figure 21 demonstrates this facility
.
Color Delay (MR23–MR25)
This control allows delay of the color signals with respect to the
falling edge of the horizontal sync signal by up to four pixel clock
cycles. Figure 21 demonstrates this facility
.
CGMS Enable (MR26)
When this bit is set to “1,” CGMS data is inserted on Line 41 in
525p mode. The CGMS conforms: to CGMS-A EIA-J CPR1204-1,
Transfer Method of Video ID information using vertical blanking
interval (525p System), March 1998 and IEC61880, 1998, video
systems (525/60)—video and accompanied data using the vertical
blanking interval—analogue interface.
The CGMS data bits are programmed into the CGMS Data
Registers 0–2. For more information refer to CGMS Data
Registers section
.
CGMS CRC (MR27)
This bit enables the automatic Cyclic Redundancy Check when
CGMS is enabled.
MAX DELAY
NO DELAY
NO DELAY
MAX DELAY
PrPb DELAY
Y DELAY
Y OUTPUT
PrPb OUTPUTS
Figure 21. Y and Color Delay
MR21
MR27
MR22
MR24
MR25
MR23
MR20
MR26
MR27
0
1
DISABLED
ENABLED
CGMS CRC
MR26
0
1
DISABLED
ENABLED
CGMS ENABLE
MR25
0
0
0
0
1
MR24
0
0
1
1
0
MR23
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
COLOR DELAY
MR22
0
0
0
0
1
MR21
0
0
1
1
0
MR20
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
Y DELAY
Figure 22. Mode Register 2
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