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參數(shù)資料
| 型號： | ADV7191KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁數(shù)： | 30/69頁 |
| 文件大?。?/td> | 628K |
| 代理商： | ADV7191KST |
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ADV7190/ADV7191
–30–
REV. 0
MODE REGISTER 2
MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Mode Register 2 is a 8-bit wide register.
Figure 52 shows the various operations under the control of Mode
Register.
MR2 BIT DESCRIPTION— RGB/YUV Control (MR20)
This bit enables the output from the small or large DACs to be
set to YUV or RGB output video standard.
DAC Output Control (MR21)
This bit controls the output from DACs A, B, and C. When this
bit is set to 1, Composite, Luma, and Chroma Signals are out-
put from DACs A, B, and C (respectively). When this bit is set
to 0, RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC out-
put configurations is shown in Table III.
Pedestal Control (MR23)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid when the device
is configured in PAL mode.
Square Pixel Control (MR24)
This bit is used to set up square pixel mode. This is available in
Slave Mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied. Square
pixel operation is not available in 4
×
Oversampling mode.
Standard I
2
C Control (MR25)
This bit controls the video standard used by the ADV7190/
ADV7191. When this bit is set to 1 the video standard as pro-
grammed in Output Video Standard Selection (MR00, MR01).
When MR25 is set to 0, the ADV7190/ADV7191 is forced into
the standard selected by the NTSC_PAL pin. When NTSC_PAL
is low the standard is NTSC, when the NTSC_PAL pin is high,
the standard is PAL.
Pixel Data Valid Control (MR26)
After resetting the device, this bit has the value 0 and the pixel
data input to the encoder is blanked such that a black screen is
output from the DACs. The ADV7190/ADV7191 will be set
to Master Mode timing. When this bit is set to 1 by the user
(via the I
2
C), pixel data passes to the pins and the encoder re-
verts to the Timing Mode defined by Timing Register 0.
Sleep Mode Control (MR27)
When this bit is set (1), Sleep Mode is enabled. With this mode
enabled, the ADV7190/ADV7191 current consumption is reduced
to less than 1 mA. The I
2
C registers can be written to and read
from when the ADV7190/ADV7191 is in Sleep Mode.
When the device is in Sleep Mode and 0 is written to MR27, the
ADV7190/ADV7191 will come out of Sleep Mode and resume
normal operation. Also, if a
RESET
is applied during Sleep
Mode, the ADV7190/ADV7191 will come out of Sleep Mode
and resume normal operation.
For this to operate, Power Up in Sleep Mode Control has to be
enabled (MR60 = 0), otherwise Sleep Mode is controlled by
the PAL_NTSC and SCRESET/RTC/TR pins.
Table III. DAC Output Configuration Matrix
SCART
MR22
DAC O/P
MR21
RGB/YUV
MR20
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
G
Y
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
B
U
LUMA
LUMA
B
U
LUMA
LUMA
R
V
CHROMA
CHROMA
R
V
CHROMA
CHROMA
CVBS
CVBS
G
Y
G
Y
G
Y
LUMA
LUMA
B
U
LUMA
LUMA
B
U
CHROMA
CHROMA
R
V
CHROMA
CHROMA
R
V
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
RGB/YUV
CONTROL
MR20
0
1
RGB OUTPUT
YUV OUTPUT
SCART ENABLE
CONTROL
MR22
0
1
DISABLE
ENABLE
SQUARE PIXEL
CONTROL
MR24
0
1
DISABLE
ENABLE
PIXEL DATA
VALID CONTROL
MR26
0
1
DISABLE
ENABLE
DAC OUTPUT
CONTROL
0
1
RGB/YUV/COMP
COMP/LUMA/CHROMA
MR21
PEDESTAL
CONTROL
0
1
PEDESTAL OFF
PEDESTAL ON
MR23
STANDARD I
2
C
CONTROL
MR25
0
1
DISABLE
ENABLE
SLEEP MODE
CONTROL
MR27
0
1
DISABLE
ENABLE
Figure 52. Mode Register 2 (MR2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7190 | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
| ADV7192KST | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7192 | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7194KST | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| ADV7194 | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7191KSTZ | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7192 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7192KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7194 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| ADV7194KST | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:PROFESSIONAL/HDTV NTSC/PAL ENCODER I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
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