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參數(shù)資料
| 型號： | ADV7185 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| 中文描述： | 專業(yè)NTSC / PAL視頻解碼器，10位CCIR656輸出 |
| 文件頁數(shù)： | 38/41頁 |
| 文件大?。?/td> | 730K |
| 代理商： | ADV7185 |
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ADV7185
Appendix
BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7185 is a highly integrated circuit containing both
precision analog and high speed digital circuitry. It has been
designed to minimize interference effects on the integrity of the
analog circuitry by the high speed digital circuitry. It is impera-
tive that these same design and layout techniques be applied to
the system level design such that high speed and accurate per-
formance are achieved. Figure 30 shows the recommended
analog circuit layout.
The layout should be optimized for lowest noise on the ADV7185
power and ground lines by shielding the digital inputs and provid-
ing good decoupling. The lead length between groups of VDD and
GND pins should be minimized to reduce inductive ringing.
Ground Planes
The ground plane should be split into two, one analog and one
digital. They should be joined directly under the ADV7185.
The analog ground return path should be through the digital
(the digital ground is connected to the analog ground and also
the system ground, whereas the analog ground is only connected
to the digital ground; this will ensure only analog current will flow
in the analog ground).
Power Planes
The ADV7185 and any associated analog circuitry should have
its own power planes, referred to as the analog and digital
power planes. These power planes should be connected to the
regular PCB power plane (V
CC
) at a single point through a ferrite
bead. This bead should be located within three inches of the
ADV7185.
The PCB power plane should provide power to all digital logic on
the PC board and the digital power pins on the ADV7185, and
the analog power plane should provide power to all analog power
pins on the ADV7185.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged so the plane-to-plane noise is common-mode.
Supply Decoupling
For optimum performance, bypass capacitors should be installed
using the shortest leads possible, consistent with reliable operation,
to reduce the lead inductance. Best performance is obtained with
0.1
μ
F ceramic capacitor decoupling. Each group of power pins
on the ADV7185 must have at least one 0.1
μ
F decoupling
capacitor to its corresponding ground. These capacitors should
be placed as close as possible to the device.
It is important to note that while the ADV7185 contains cir-
cuitry to reject power supply noise, this rejection decreases with
frequency. If a high-frequency switching power supply is used,
the designer should pay close attention to reducing power sup-
ply noise and consider using a three-terminal voltage regulator
for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs and outputs to and from the ADV7185 should
be isolated as much as possible from the analog inputs and other
analog circuitry. Also, these input signals should not overlay the
analog power plane.
Due to the high clock rates involved, long clock lines to and
from the ADV7185 should be avoided to reduce noise pickup.
Any series termination resistors (typically 33R) for the digital
inputs should be connected to the high speed digital outputs.
Analog Signal Interconnect
The ADV7185 should be located as close as possible to the
input connectors to minimize noise pickup and reflections due
to impedance mismatch.
The video input signals should overlay the ground plane, and
not the analog power plane, to maximize the high-frequency
power supply rejection.
Digital outputs, especially pixel data Inputs and clocking sig-
nals, should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
The ADV7185 should have no inputs left floating. Any inputs
that are not required should be tied to ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7185KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| ADV7186 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Decoder and Display Processor |
| ADV7186BBCZ | 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ADV7186BBCZ-RL | 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ADV7186BBCZ-T | 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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