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參數(shù)資料
| 型號(hào)： | ADV7181DWBCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER SD/HD 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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ADV7181D
Data Sheet
Rev. A | Page 16 of 24
Table 8 provides the recommended ADC mapping for the ADV7181D.
Table 8. Recommended ADC Mapping
Mode
Required ADC Mapping
Analog Input Channel
Core
Configuration1
CVBS
ADC0
CVBS = A
IN1
SDP
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
YC/YC Auto
Y = ADC0
C = ADC1
Y = A
IN7
C = A
IN9
SDP
INSEL[3:0] = 0000
SDM_SEL[1:0] = 11
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
Component YUV
Y = ADC0
U = ADC2
V = ADC1
Y = A
IN10
U = A
IN8
V = A
IN6
SDP
INSEL[3:0] = 1001
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
Component YUV
Y = ADC0
U = ADC2
V = ADC1
Y = A
IN10
U = A
IN8
V = A
IN6
CP
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 1010
SCART RGB
CBVS = ADC0
G = ADC1
B = ADC3
R = ADC2
CVBS = A
IN4
G = A
IN10
B = A
IN6
R = A
IN8
SDP
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
Graphics
RGB Mode
G = ADC0
B = ADC2
R = ADC1
G = A
IN2
B = A
IN3
R = A
IN5
CP
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0010
VID_STD[3:0] = 1100
1 Configuration to format follow-on blocks in correct frame.
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