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參數(shù)資料
| 型號： | ADV7181CBSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER SDTV RGB 64LQFP |
| 標準包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應用： | HDTV |
| 電壓 - 電源，模擬： | 3.15 V ~ 3.45 V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 2 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
ADV7181C
Data Sheet
Rev. E | Page 6 of 20
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = 40°C to +85°C,
unless otherwise noted.
Table 3.
Parameter1, 2
Symbol
Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
28.63636
MHz
Crystal Frequency Stability
±50
ppm
Horizontal Sync Input Frequency
14.8
110
kHz
LLC Frequency Range
12.825
110
MHz
SCLK Frequency
400
kHz
SCLK Minimum Pulse Width High
t
1
0.6
s
SCLK Minimum Pulse Width Low
t
2
1.3
s
Hold Time (Start Condition)
t
3
0.6
s
Setup Time (Start Condition)
t
4
0.6
s
SDA Setup Time
t
5
100
ns
SCLK and SDA Rise Time
t
6
300
ns
SCLK and SDA Fall Time
t
7
300
ns
Setup Time for Stop Condition
t
8
0.6
s
RESET FEATURE
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC Mark Space Ratio
t
9:t10
45:55
55:45
% duty cycle
DATA AND CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)4
t
11
Negative clock edge
to start of valid data
3.6
ns
Data Output Transition Time SDR (SDP)4
t
12
End of valid data to
negative clock edge
2.4
ns
Data Output Transition Time SDR (CP)5
t
13
End of valid data to
negative clock edge
2.8
ns
Data Output Transition Time SDR (CP)5
t
14
Negative clock edge
to start of valid data
0.1
ns
Data Output Transition Time DDR (CP)5, 6
t
15
Positive clock edge
to end of valid data
1.9
ns
Data Output Transition Time DDR (CP)5, 6
t
16
Start of valid data to
positive clock edge
1.7
ns
Data Output Transition Time DDR (CP)5, 6
t
17
Negative clock edge
to end of valid data
1.4
ns
Data Output Transition Time DDR (CP)5, 6
t
18
Start of valid data to
negative clock edge
1.7
ns
1 The minimum/maximum specifications are guaranteed over this range.
2 Guaranteed by characterization.
3 TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.
4 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
5 CP timing figures obtained using maximum drive strength value (0x3F) in Register Subaddress 0xF4.
6 Guaranteed by characterization up to 75 MHz pixel clock.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7181CBSTZ-REEL | 功能描述:IC VIDEO DECODER SDTV RGB 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7181CWBSTZ | 制造商:Analog Devices 功能描述:Video Decoder 4ADC 10-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:10-BIT, INTEGRATED, MULTIFORMAT SDTV VIDEO DECODER AND RGB G - Rail/Tube |
| ADV7181CWBSTZ-REEL | 功能描述:Video Decoder IC HDTV 64-LQFP (10x10) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:視頻解碼器 應用:HDTV 電壓 - 電源，模擬:3.15 V ~ 3.45 V 電壓 - 電源，數(shù)字:1.65 V ~ 2 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商器件封裝:64-LQFP（10x10） 標準包裝:1,500 |
| ADV7181D | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 10-Channel, Multiformat SDTV/HDTV |
| ADV7181DBCPZ | 制造商:Analog Devices 功能描述:10-BIT, 10 CHANNEL MULTIFORMAT SDTV/HDTV VIDEO DECODER AND R - Trays 制造商:Analog Devices 功能描述:10-BIT SD/HD VIDEO DECODER |
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