參數(shù)資料
型號: ADV7180WBCPZ
廠商: Analog Devices Inc
文件頁數(shù): 78/116頁
文件大?。?/td> 0K
描述: IC VIDEO DECODER SDTV 40LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 視頻解碼器
應(yīng)用: 數(shù)碼相機(jī),手機(jī),便攜式視頻
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 托盤
ADV7180
Data Sheet
Rev. I | Page 64 of 116
CGMS and WSS
The CGMS and WSS data packets convey the same type of
information for different video standards. WSS is for PAL and
CGMS is for NTSC; therefore, the CGMS and WSS readback
registers are shared. WSS is biphase coded; the VDP performs a
biphase decoding to produce the 14 raw WSS bits in the CGMS/
WSS readback I2C registers and to set the CGMS_WSS_AVL bit.
CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78[2],
User Sub Map, Write Only, Self-Clearing
Setting CGMS_WSS_CLEAR to 1 reinitializes the CGMS/WSS
readback registers.
CGMS_WSS_AVL, CGMS/WSS Available, Address 0x78[2],
User Sub Map, Read Only
When CGMS_WSS_AVL is 0, CGMS/WSS is not detected.
When CGMS_WSS_AVL is 1, CGMS/WSS is detected.
VDP_CGMS_WSS_DATA_0[3:0], Address 0x7D[3:0];
VDP_CGMS_WSS_DATA_1[7:0], Address 0x7E[7:0];
VDP_CGMS_WSS_DATA_2[7:0], Address 0x7F[7:0];
User Sub Map, Read Only
These bits hold the decoded CGMS or WSS data.
Refer to Figure 48 and Figure 49 for the I2C-to-WSS and I2C-to-
CGMS bit mapping.
05700-
039
ACTIVE
VIDEO
VDP_CGMS_WSS_
DATA_1[5:0]
VDP_CGMS_WSS_DATA_2
RUN-IN
SEQUENCE
START
CODE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
11.0s
38.4s
42.5s
Figure 48. WSS Waveform
05700-
040
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
VDP_CGMS_WSS_DATA_1
VDP_CGMS_WSS_
DATA_0[3:0]
VDP_CGMS_WSS_DATA_2
REF
+100 IRE
+70 IRE
0 IRE
–40 IRE
11.2s
49.1s ± 0.5s
CRC SEQUENCE
2.235s ± 20ns
Figure 49. CGMS Waveform
Table 81. CGMS Readback Registers1
Signal Name
Register Location
Address (User Sub Map)
CGMS_WSS_DATA_0[3:0]
VDP_CGMS_WSS_DATA_0[3:0]
125
0x7D
CGMS_WSS_DATA_1[7:0]
VDP_CGMS_WSS_DATA_1[7:0]
126
0x7E
CGMS_WSS_DATA_2[7:0]
VDP_CGMS_WSS_DATA_2[7:0]
127
0x7F
1
These registers are readback registers; default value does not apply.
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