參數(shù)資料
型號(hào)： ADV7180
廠商： Analog Devices, Inc.
英文描述： 10-Bit, 4 x Oversampling SDTV Video Decoder
中文描述： 10位，4個(gè)采樣標(biāo)清視頻解碼器
文件頁(yè)數(shù)： 48/112頁(yè)
文件大?。?/td> 1320K
代理商： ADV7180
ADV7180
Rev. A | Page 48 of 112
FIELD 1
622
623
624
625
1
2
3
4
5
6
7
8
9
10
11
23
24
310
311
312
313
314
315
316
317
318
319
320
321
322
323
336
337
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4
PFTOG[4:0] = 0x6
FIELD 2
OUTPUT
VIDEO
FIELD
OUTPUT
HS
OUTPUT
VS
OUTPUT
OUTPUT
VIDEO
FIELD
OUTPUT
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4
PFTOG[4:0] = 0x6
0
Figure 39. PAL Typical VS/FIELD Positions Using Register Writes Shown in Table 62
PVBEG[4:0], PAL Vsync Begin, Address 0xE8 [4:0]
The default value of PVBEG is 00101, indicating the PAL vsync
begin position. For all NTSC/PAL vsync timing controls, the
V bit in the AV code and the vsync on the VS pin are modified.
Table 62. User Settings for PAL
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE8
0xE9
0xEA
Register Name
VS/FIELD Control 1
VS/FIELD Control 2
VS/FIELD Control 3
HS Position Control 1
HS Position Control 2
HS Position Control 3
Polarity
PAL V Bit Begin
PAL V Bit End
PAL F Bit Toggle
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
VSYNC BEGIN
PVBEGSIGN
ODD FIELD
0
1
NO
YES
PVBEGDELO
VSBHO
DELAY BY
1 LINE
A0.5 LINE
1
0
1
0
PVBEGDELE
VSBHE
DELAY BY
1 LINE
A0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
0
PVBEGDELO, PAL Vsync Begin Delay on Odd Field,
Address 0xE8 [7]
When PVBEGDELO is 0 (default), there is no delay.
Setting PVBEGDELO to 1 delays vsync going high on an odd
field by a line relative to PVBEG.
PVBEGDELE PAL, Vsync Begin Delay on Even Field,
Address 0xE8 [6]
When PVBEGDELE is 0, there is no delay.
Setting PVBEGDELE to 1 (default) delays vsync going high on
an even field by a line relative to PVBEG.
PVBEGSIGN PAL, Vsync Begin Sign, Address 0xE8 [5]
Setting PVBEGSIGN to 0 delays the beginning of vsync. Set for
user manual programming.
Setting PVBEGSIGN to 1(default) advances the beginning of
vsync. Not recommended for user programming.
Figure 40. PAL Vsync Begin
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7180_12 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 4?? Oversampling SDTV Video Decoder
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ADV7180BCP32Z-RL 制造商:Analog Devices 功能描述:IC
ADV7180BCPZ 功能描述:IC VIDEO DECODER SDTV 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND
ADV7180BCPZ 制造商:Analog Devices 功能描述:IC VIDEO DECODER 10BIT 57.27MSPS LFCSP40
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