參數(shù)資料
型號(hào)： ADV7179BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/52頁(yè)
文件大?。?/td> 0K
描述： IC ENCODER VID NTSC/PAL 40LFCSP
產(chǎn)品培訓(xùn)模塊： Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
電壓 - 電源，模擬： 2.8 V，3.3 V
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 786 (CN2011-ZH PDF)
ADV7174/ADV7179
Rev. B | Page 34 of 52
TIMING MODE REGISTER 1 (TR1)
Bits:
TR17–TR10
Address:
SR4–SR0 = 08H
Timing Register 1 is an 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register
can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.
TR11
TR10
TR17
TR12
TR13
TR15
TR16
TR14
HSYNC TO PIXEL
DATA ADJUST
TR17 TR16
00
× T
PCLK
1
× T
PCLK
1
× T
PCLK
4
× T
PCLK
16
× T
PCLK
128
× T
PCLK
0
× T
PCLK
4
× T
PCLK
8
× T
PCLK
16
× T
PCLK
1
× T
PCLK
4
× T
PCLK
16
× T
PCLK
128
× T
PCLK
2
× T
PCLK
3
× T
PCLK
0
1
0
1
0
1
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
0
1
0
1
0
1
HSYNC WIDTH
0
1
0
1
0
1
TR11 TR10
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
xTB
TB + 32μs
x
0
1
TR15 TR14
TC
TA
TB
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
1
0
1
0
1
LINE 313
LINE 314
LINE 1
TIMING MODE 1 (MASTER/PAL)
HSYNC
FIELD/VSYNC
TB
TA
TC
02980-A
-043
Figure 44. Timing Register 1
Table 16. TR1 Bit Description
Bit Name
Bit No.
Description
These bits adjust the HSYNC pulse width.
HSYNC Width
TR11–TR10
These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output.
HSYNC to FIELD/VSYNC
Delay
TR13–TR12
When the ADV7174/ADV7179 is in Timing Mode 1, these bits adjust the position of the HSYNC
output relative to the FIELD output rising edge.
HSYNC to FIELD Rising
Edge Delay
TR15–TR14
When the ADV7174/ADV7179 is configured in Timing Mode 2, these bits adjust the VSYNC
pulse width.
VSYNC Width
TR15–TR14
This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb
components to be swapped. This adjustment is available in both master and slave timing modes.
HSYNC to Pixel Data Adjust
TR17–TR16
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