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參數(shù)資料
| 型號： | ADV7173KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 35/59頁 |
| 文件大?。?/td> | 455K |
| 代理商： | ADV7173KST |
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ADV7172/ADV7173
–35–
REV. A
TIMING REGISTER 1 (TR17–TR10)
(Address (SR4–SR0) = 0BH)
Timing Register 1 is an 8-bit-wide register.
Figure 53 shows the various operations under the control of
Timing Register 1. This register can be read from as well writ-
ten to. This register can be used to adjust the width and posi-
tion of the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC
Width (TR11–TR10)
These bits adjust the
HSYNC
pulsewidth.
HSYNC
to FIELD/
VSYNC
Delay Control (TR13–TR12)
These bits adjust the position of the
HSYNC
output relative to
the FIELD/
VSYNC
output.
TR11
TR10
TR17
TR12
TR13
TR15
TR16
TR14
HSYNC
TO PIXEL
DATA ADJUSTMENT
TR17 TR16
0
0
1
1
0
1
0
1
0
3
T
PCLK
1
3
T
PCLK
2
3
T
PCLK
3
3
T
PCLK
HSYNC
TO
FIELD/
VSYNC
DELAY
TR13 TR12
0
0
1
1
0
1
0
1
0
3
T
PCLK
4
3
T
PCLK
8
3
T
PCLK
16
3
T
PCLK
T
B
HSYNC
WIDTH
TR11 TR10
0
0
1
1
0
1
0
1
1
3
T
PCLK
4
3
T
PCLK
16
3
T
PCLK
128
3
T
PCLK
T
A
HSYNC
TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
x
x
0
1
T
B
T
B
+ 32
m
s
TR15 TR14
T
C
VSYNC
WIDTH
(MODE 2 ONLY)
0
0
1
1
0
1
0
1
1
3
T
PCLK
4
3
T
PCLK
16
3
T
PCLK
128
3
T
PCLK
LINE 313
LINE 314
LINE 1
T
B
TIMING MODE 1 (MASTER/PAL)
HSYNC
FIELD/
VSYNC
T
A
T
C
TR15 TR14
Figure 53. Timing Register 1
HSYNC
to FIELD Delay Control (TR15–TR14)
When the ADV7172/ADV7173 is in Timing Mode 1, these bits
adjust the position of the
HSYNC
output relative to the FIELD
output rising edge.
VSYNC
Width (TR15–TR14)
When the ADV7172/ADV7173 is configured in Timing Mode
2, these bits adjust the
VSYNC
pulsewidth.
HSYNC
to Pixel Data Adjust (TR17–TR16)
This enables the
HSYNC
to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7172KST | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| ADV7172 | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| ADV7173 | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| ADV7173* | Digital PAL/NTSC Video Encoder with Six DACs (10 Bits). Color Control and Enhanced Power Management |
| ADV7174 | Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7173KST-REEL | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 48-Pin LQFP T/R |
| ADV7173KSTZ | 功能描述:IC DAC VIDEO NTSC 6-CH 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7173KSTZ-REEL | 功能描述:IC DAC VIDEO NTSC 6-CH 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7174 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| ADV7174BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
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