參數(shù)資料
型號(hào): ADV7170
廠商: Analog Devices, Inc.
英文描述: Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management
中文描述: 數(shù)碼PAL / NTSC視頻編碼器與10位SSAF⑩和高級(jí)電源管理
文件頁數(shù): 31/55頁
文件大?。?/td> 754K
代理商: ADV7170
ADV7170/ADV7171
–31–
REV. 0
75
V
27
26
S VIDEO
31
32
5k
V
+5V (V
CC
)
150
V
24
5k
V
+5V (V
CC
)
MPU BUS
44
22
15
17
16
10, 19, 21
29, 43
18
23
34
38–42,
2–9, 12–14
1, 11, 20, 28, 30
0.1
m
F
0.01
m
F
0.1
m
F
+5V (V
AA
)
0.1
m
F
+5V (V
AA
)
10k
V
+5V (V
AA
)
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
10
m
F
33
m
F
GND
L1
(FERRITE BEAD)
+5V
(V
CC
)
25
33
GND
ALSB
HSYNC
FIELD/
VSYNC
BLANK
RESET
CLOCK
R
SET
SDATA
SCLOCK
DAC B
DAC C
DAC D
V
AA
V
REF
COMP
P15–P0
+5V (V
AA
)
75
V
75
V
75
V
35 SCRESET/RTC
ADV7170/
ADV7171
“UNUSED
INPUTS
SHOULD BE
GROUNDED”
DAC A
100
V
100
V
4k
V
+5V (V
AA
)
100nF
RESET
37 TTX
36 TTXREQ
100k
V
100k
V
+5V (V
AA
)
TTX
TTXREQ
TELETEXT PULL-UP AND
PULL-DOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
Figure 54. Recommended Analog Circuit Layout
The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the
HSYNC
pulse. This waveform
is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if
13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the
ADV7170/ADV7171 in the correct sequence.
D
Q
CK
D
Q
CK
CLOCK
HSYNC
13.5MHz
Figure 55. Circuit to Generate 13.5 MHz
相關(guān)PDF資料
PDF描述
ADV7170KS Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management
ADV7170SU Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management
ADV7171KS Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management
ADV7171SU Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management
ADV7171* Digital PAL/NTSC Video Encoder with 10-Bit SSAF and Advanced Power Management
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