
REV. 0
–38–
ADV7160/ADV7162
APPENDIX 4
INITIALIZATION AND PROGRAMMING
ADV7160/ADV7162 INITIALIZATION
After power has been supplied, the ADV7160/ADV7162 must be initialized. The Mode Register and Control Registers must then
be set up. The values written to the various registers will be determined by the desired operating mode of the part, i.e., True-Color/
Pseudo-Color, 4:1 Muxing/2:1 Muxing, PLL on/off, Bypass Mode on/off etc.. . .
The following section gives a recommended initialization of the ADV7160/ADV7162 and an example of the ADV7162 operating in a
specific mode.
ADV7160/ADV7162 Initialization
Write (xx000xx1)* to Mode Register (MR1)
Write (xx000xx0)* to Mode Register (MR1)
Write (xx000xx1)* to Mode Register (MR1)
Write 05H to Address Register (A7–A0)
Write (xxxx100x)* to Command Register 1 (CR1)
Write 06H to Address Register (A7–A0)
Write 00H to Address Register (A10–A8)
Write (xxxxxx00)* to Command Reg 2 (CR2)
Write 07H to Address Register (A7–A0)
Write 00H to Address Register (A10–A8)
Write (xx0xxxxx)* to Command Reg 3 (CR3)
Write 08H to Address Register (A7–A0)
Write 00H to Address Register (A10–A8)
Write (xxxxxxxx)* to Command Reg 4 (CR4)
Write 0DH to Address Register (A7–A0)
Write 00H to Address Register (A10–A8)
Write (0x000000)* to Command Reg 5 (CR5)
Write 04H to Address Register (A7–A0)
Write 00H to Address Register (A10–A8)
Write (xxxxxxxx)* to Pixel Mask Register
Write 04H to Address Register (A7–A0)
Write 02H to Address Register (A10–A8)
Write (xxxxxxxx)* to Cursor Control Register
Write 0FH to Address Register (A7–A0)
Write 00H to Address Register (A10–A8)
Write (xxxxxxxx)* to PLL V Register
Write 0CH to Address Register (A7–A0)
Write 00H to Address Register (A10–A8)
Write (xxxx0xxx)* to PLL R Register
Write 09H to Address Register (A7–A0)
Write 00H to Address Register (A10–A8)
Write (xxxxxxxx)* to PLLCommand Register
Write (xx0xxxxx)* to Mode Register (MR1)
Write (xx1xxxxx)* to Mode Register (MR1)
Write (xx0xxxxx)* to Mode Register (MR1)
C1 C0
1
1
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
R/
W
Comment
0
Resets ADV7160/62
0
0
0
Address Reg points to Command Register 1 (CR1)
0
Address Reg points to CR1 for high byte access
0
0
Address Reg points to Command Register 2 (CR2)
0
Setup CR2 as required
0
0
Address Reg points to Command Register 3 (CR3)
0
Setup CR3 as required
0
0
Address Reg points to Command Register 4 (CR4)
0
Setup CR4 as required
0
0
Address Reg points to Command Register 5 (CR5)
0
Setup CR 5 as required
0
0
Address Reg points to Pixel Mask Register
0
Set up Pixel Mask as required
0
Necessary only if CCR to be used
0
Address Reg points to Cursor Control Register (CCR)
0
Set up CCR as required
0
Necessary only if PLL to be used
0
Address Reg points to PLL V Register
0
Set up V as required
0
Necessary only if PLL to be used
0
Address Reg points to PLL R Register
0
Set up R as required
0
Necessary only if PLL to be used
0
Address Reg points to PLL Command Register (PCR)
0
Set up PCR as required
0
Necessary only if manual claibration is required
0
Toggles MR15
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
*x represents either a 0 or 1 value that the bit should be set to, depending on the desired operating mode of the ADV7160/ADV7162.