參數(shù)資料
型號(hào): ADV7127KRUZ50
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 7/16頁(yè)
文件大小: 0K
描述: IC DAC VIDEO SGL HI SPD 24-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 62
設(shè)置時(shí)間: 15ns
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 30mW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
輸出數(shù)目和類(lèi)型: 2 電流,單極
采樣率(每秒): 240M
ADV7127
–15–
REV. 0
Digital Signal Interconnect
The digital signal lines to the ADV7127 should be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines should not overlay the analog
power plane.
Due to the high clock rates used, long clock lines to the ADV7127
should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (VCC), and
not the analog power plane.
Analog Signal Interconnect
The ADV7127 should be located as close as possible to the
output connectors thus minimizing noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75
(doubly
terminated 75
configuration). This termination resistance
should be as close as possible to the ADV7127 so as to mini-
mize reflections.
Additional information on PCB design is available in an applica-
tion note entitled “Design and Layout of a Video Graphics
System for Reduced EMI.” This application note is available
from Analog Devices, publication number E1309-15-10/89.
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