參數(shù)資料
型號： ADV7123KST50
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： CMOS, 240 MHz Triple 10-Bit High Speed Video DAC
中文描述： PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48
封裝： PLASTIC, LQFP-48
文件頁數(shù)： 4/20頁
文件大小： 342K
代理商： ADV7123KST50
ADV7123
5 V DYNAMIC SPECIFICATIONS
1
–4–
REV. B
Parameter
Min
Typ
Max
Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
2
Single-Ended Output
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz
f
CLK
= 50 MHz; f
OUT
= 2.51 MHz
f
CLK
= 50 MHz; f
OUT
= 5.04 MHz
f
CLK
= 50 MHz; f
OUT
= 20.2 MHz
f
CLK
= 100 MHz; f
OUT
= 2.51 MHz
f
CLK
= 100 MHz; f
OUT
= 5.04 MHz
f
CLK
= 100 MHz; f
OUT
= 20.2 MHz
f
CLK
= 100 MHz; f
OUT
= 40.4 MHz
f
CLK
= 140 MHz; f
OUT
= 2.51 MHz
f
CLK
= 140 MHz; f
OUT
= 5.04 MHz
f
CLK
= 140 MHz; f
OUT
= 20.2 MHz
f
CLK
= 140 MHz; f
OUT
= 40.4 MHz
Double-Ended Output
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz
f
CLK
= 50 MHz; f
OUT
= 2.51 MHz
f
CLK
= 50 MHz; f
OUT
= 5.04 MHz
f
CLK
= 50 MHz; f
OUT
= 20.2 MHz
f
CLK
= 100 MHz; f
OUT
= 2.51 MHz
f
CLK
= 100 MHz; f
OUT
= 5.04 MHz
f
CLK
= 100 MHz; f
OUT
= 20.2 MHz
f
CLK
= 100 MHz; f
OUT
= 40.4 MHz
f
CLK
= 140 MHz; f
OUT
= 2.51 MHz
f
CLK
= 140 MHz; f
OUT
= 5.04 MHz
f
CLK
= 140 MHz; f
OUT
= 20.2 MHz
f
CLK
= 140 MHz; f
OUT
= 40.4 MHz
Spurious-Free Dynamic Range within a Window
Single-Ended Output
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz; 1 MHz Span
f
CLK
= 50 MHz; f
OUT
= 5.04 MHz; 2 MHz Span
f
CLK
= 140 MHz; f
OUT
= 5.04 MHz; 4 MHz Span
Double-Ended Output
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz; 1 MHz Span
f
CLK
= 50 MHz; f
OUT
= 5.00 MHz; 2 MHz Span
f
CLK
= 140 MHz; f
OUT
= 5.00 MHz; 4 MHz Span
Total Harmonic Distortion
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz
T
A
= 25
°
C
T
MIN
to T
MAX
f
CLK
= 50 MHz; f
OUT
= 2.00 MHz
f
CLK
= 100 MHz; f
OUT
= 2.00 MHz
f
CLK
= 140 MHz; f
OUT
= 2.00 MHz
DAC PERFORMANCE
Glitch Impulse
DAC Crosstalk
3
Data Feedthrough
4, 5
Clock Feedthrough
4, 5
67
67
63
55
62
60
54
48
57
58
52
41
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
70
70
65
54
67
63
58
52
62
61
55
53
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
77
73
64
dBc
dBc
dBc
74
73
60
dBc
dBc
dBc
66
65
64
63
55
dBc
dBc
dBc
dBc
dBc
10
23
22
33
pVs
dB
dB
dB
NOTES
1
These maximum/minimum specifications are guaranteed by characterization over the 4.75 V to 5.25 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
.
3
DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of –3 ns, measured from the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
Specifications subject to change without notice.
(V
AA
= 5 V 5%
1
, V
REF
= 1.235 V, R
SET
= 560 , C
L
= 10 pF. All specifications are
T
A
= 25 C, unless otherwise noted, T
J
MAX
= 110 C.)
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