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參數(shù)資料
| 型號： | ADV7123JSTZ240 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO TRPL HI SPD 48-LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 6 電流，單極 |
| 采樣率（每秒）： | 240M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
ADV7123
Rev. D | Page 8 of 24
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 6.
Parameter3
Symbol
Min
Typ
Max
Unit
Conditions
ANALOG OUTPUTS
Analog Output Delay
t6
7.5
ns
Analog Output Rise/Fall Time4
t7
1.0
ns
Analog Output Transition Time5
t8
15
ns
Analog Output Skew6
t9
1 2
ns
CLOCK CONTROL
CLOCK Frequency7
fCLK
50
MHz
50 MHz grade
140
MHz
140 MHz grade
240
MHz
240 MHz grade
330
MHz
330 MHz grade
Data and Control Setup
t1
0.2
ns
Data and Control Hold
t2
1.5
ns
CLOCK Period
t3
3
ns
CLOCK Pulse Width High6
t4
1.4
ns
fCLK_MAX = 330 MHz
CLOCK Pulse Width Low6
t5
1.4
ns
fCLK_MAX = 330 MHz
CLOCK Pulse Width High
t4
1.875
ns
fCLK_MAX = 240 MHz
CLOCK Pulse Width Low
t5
1.875
ns
fCLK_MAX = 240 MHz
CLOCK Pulse Width High
t4
2.85
ns
fCLK_MAX = 140 MHz
CLOCK Pulse Width Low
t5
2.85
ns
fCLK_MAX = 140 MHz
CLOCK Pulse Width High
t4
8.0
ns
fCLK_MAX = 50 MHz
CLOCK Pulse Width Low
t5
8.0
ns
fCLK_MAX = 50 MHz
Pipeline Delay6
tPD
1.0
Clock cycles
PSAVE Up Time6
t10
4
10
ns
1 These maximum and minimum specifications are guaranteed over this range.
2 Temperature range: TMIN to TMAX: 40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
t3
t1
t4
t8
t2
t6
t7
t5
CLOCK
DIGITAL INPUTS
(R9 TO R0, G9 TO G0, B9 TO B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
NOTES
1. OUTPUT DELAY (
t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (
t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
00
21
5-
0
02
Figure 2. Timing Diagram
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