RSET A resistor (R
參數(shù)資料
型號: ADV7123JSTZ240-RL
廠商: Analog Devices Inc
文件頁數(shù): 3/24頁
文件大?。?/td> 0K
描述: IC DAC VIDEO 3-CH 240MHZ 48LQFP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 2,000
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
電壓電源: 單電源
功率耗散(最大): 30mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 6 電流,單極
采樣率(每秒): 240M
ADV7123
Rev. D | Page 11 of 24
Pin No.
Mnemonic
Description
37
RSET
A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal.
Note that the IRE relationships are maintained, regardless of the full-scale output current. For nominal video
levels into a doubly terminated 75 Ω load, RSET = 530 Ω. The relationship between RSET and the full-scale
output current on IOG (assuming ISYNC is connected to IOG) is given by:
RSET (Ω) = 11,445 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG (mA) = 11,445 × VREF (V)/RSET (Ω) (SYNC being asserted)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied
permanently low.
38
PSAVE
Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active.
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