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參數(shù)資料
| 型號(hào)： | ADV7123 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS, 240 MHz Triple 10-Bit High Speed Video DAC(240MHz三通道10位高速視頻D/A轉(zhuǎn)換器) |
| 中文描述： | 的CMOS，240 MHz的三路10位高速視頻DAC（240MHz的三通道10位高速視頻的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 318K |
| 代理商： | ADV7123 |
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ADV7123
–9–
REV. A
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
BLANK
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs,
IOR, IOB and IOG, to the blanking level. The
BLANK
signal is latched on the rising edge of CLOCK. While
BLANK
is a logical zero, the R0–R9, G0–G9 and R0–R9 pixel inputs are ignored.
Composite sync control input (TTL compatible). A logical zero on the
SYNC
input switches off a 40 IRE
current source. This is internally connected to the IOG analog output.
SYNC
does not override any other
control or data input, therefore, it should only be asserted during the blanking interval.
SYNC
is latched on the
rising edge of CLOCK.
If sync information is not required on the green channel, the
SYNC
input should be tied to logical zero.
Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9,
SYNC
and
BLANK
pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be
driven by a dedicated TTL buffer.
Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK.
R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular PCB power or ground plane.
Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75
coaxial cable. All three current outputs should have similar output loads whether or not
they are all being used.
Differential red, green and blue current outputs (high impedance current sources). These RGB video outputs
are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75
load. If the
complementary outputs are not required, these outputs should be tied to ground.
Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active.
A resistor (R
SET
) connected between this pin and GND, controls the magnitude of the full-scale video signal.
Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between R
SET
and the full-scale output current on IOG (assuming I
SYNC
is connected to IOG)
is given by:
R
SET
(
)
= 12,081
×
V
REF
(V)/IOG (mA)
The relationship between R
SET
and the full-scale output current on IOR, IOG and IOB is given by:
IOG (mA)
= 12,081
×
V
REF
(V)/R
SET
(
) (
SYNC
being asserted)
IOR, IOB (mA)
= 8,627
×
V
REF
(V)/R
SET
(
)
The equation for IOG will be the same as that for IOR and IOB when
SYNC
is not being used, i.e.,
SYNC
tied permanently low.
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1
μ
F ceramic capacitor
must be connected between COMP and V
AA
.
Voltage reference input for DACs or voltage reference output (1.235 V)
Analog power supply (5 V
±
5%). All V
AA
pins on the ADV7123 must be connected.
Ground. All GND pins must be connected.
SYNC
CLOCK
R0–R9,
G0–G9,
B0–B9
IOR, IOG, IOB
IOR
,
IOG
,
IOB
PSAVE
R
SET
COMP
V
REF
V
AA
GND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7123JST240 | 制造商:Rochester Electronics LLC 功能描述:TRIPLE HIGH SPEED VIDEO DAC I.C. - Bulk 制造商:Analog Devices 功能描述:IC 10-BIT VIDEO DAC |
| ADV7123JST240-REEL | 制造商:Rochester Electronics LLC 功能描述:TRIPLE HIGH SPEED VIDEO DAC I.C. - Tape and Reel 制造商:Analog Devices 功能描述: |
| ADV7123JST330 | 制造商:Rochester Electronics LLC 功能描述:TRIPLE HIGH SPEED VIDEO DAC I.C. - Bulk 制造商:Analog Devices 功能描述:IC 10-BIT VIDEO DAC |
| ADV7123JSTZ240 | 功能描述:IC DAC VIDEO TRPL HI SPD 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| ADV7123JSTZ240 | 制造商:Analog Devices 功能描述:D/A Converter (D-A) IC |
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