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參數(shù)資料
| 型號： | ADV7120KSTZ50 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO 3-CH 50MHZ 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 12ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 625mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 3 電流，單極 |
| 采樣率（每秒）： | 50M |
ADV7120
REV. B
–9–
The unused analog outputs should be terminated with the same
load as that for the used channel. In other words, if the red
channel is used and IOR is terminated with a doubly terminated
75
load (37.5 ), IOB and IOG should be terminated with
37.5
resistors. (See Figure 6.)
GND
ADV7120
R0
R7
G0
G7
B0
B7
VIDEO
INPUT
DOUBLY
TERMINATED
75
LOAD
IOR
IOG
IOB
37.5
37.5
Figure 6. Input and Output Connections for Stand-Alone
Gray Scale or Composite Video
Video Output Buffers
The ADV7120 is specified to drive transmission line loads,
which is what most monitors are rated as. The analog output
configurations to drive such loads are described in the Analog
Interface section and illustrated in Figure 5. However, in some
applications it may be required to drive long “transmission line”
cable lengths. Cable lengths greater than 10 meters can attenu-
ate and distort high frequency analog output pulses. The inclu-
sion of output buffers will compensate for some cable distortion.
Buffers with large full power bandwidths and gains between 2
and 4 will be required.
These buffers will also need to be able to supply sufficient cur-
rent over the complete output voltage swing. Analog Devices
produces a range of suitable op amps for such applications.
These include the AD84X series of monolithic op amps. In very
high frequency applications (80 MHz), the AD9617 is recom-
mended. More information on line driver buffering circuits is
given in the relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit will result in any desired
video level.
7
6
4
3
2
AD848
DACs
IOR, IOG, IOB
(CABLE)
Z
O = 75
Z
S = 75
(SOURCE
TERMINATION)
Z
L = 75
(MONITOR)
0.1
F
75
+V
S
Z
1
Z
2
–V
S
0.1
F
GAIN (G) = 1 +
Z
1
Z
2
Figure 7. AD848 As an Output Buffer
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