參數(shù)資料
型號: ADV7120KPZ30
廠商: Analog Devices Inc
文件頁數(shù): 9/12頁
文件大?。?/td> 0K
描述: IC DAC VIDEO 3CH 30MHZ 44PLCC
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
設置時間: 12ns
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
電壓電源: 單電源
功率耗散(最大): 625mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
輸出數(shù)目和類型: 3 電流,單極
采樣率(每秒): 30M
ADV7120
REV. B
–6–
TERMINOLOGY
Blanking Level
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
Color Video (RGB)
This usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Sync Signal (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different lev-
els while a 6-bit DAC contains 64.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Level
The peak level of the SYNC signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
CIRCUIT DESCRIPTION AND OPERATION
The ADV7120 contains three 8-bit D/A converters, with three
input channels each containing an 8-bit register. Also inte-
grated on board the part is a reference amplifier and CRT con-
trol functions BLANK, SYNC and REF WHITE.
Digital Inputs
24-bits of pixel data (color information) R0–R7, G0–G7 and
B0–B7 are latched into the device on the rising edge of each
clock cycle. This data is presented to the three 8-bit DACs and
is then converted to three analog (RGB) output waveforms.
(See Figure 2.)
Three other digital control signals are latched to the analog
video outputs in a similar fashion. BLANK, SYNC and REF
WHITE are each latched on the rising edge of CLOCK to
maintain synchronization with the pixel data stream.
The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK
and SYNC digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV7120. The influence
of SYNC and BLANK on the analog video waveform is
illustrated.
The REF WHITE control input drives the RGB video outputs
to the white level. This function could be used to overlay a cur-
sor or crosshair onto the RGB video output.
Table I details the resultant effect on the analog outputs of
BLANK
, SYNC and REF WHITE.
All these digital inputs are specified to accept TTL logic levels.
Clock Input
The CLOCK input of the ADV7120 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following
equation:
Dot Rate = (Horiz: Res)
× (Vert Res) × (Refresh Rate)/
(Retrace Factor)
Horiz Res
=
Number of pixels/line
Vert Res
=
Number of lines/frame
Refresh Rate
=
Horizontal scan rate. This is the rate at
which the screen must be refreshed, typi-
cally 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.
Retrace Factor
=
Total blank time factor. This takes into ac-
count that the display is blanked for a cer-
tain fraction of the total duration of each
frame (e.g., 0.8).
CLOCK
ANALOG OUTPUTS
(IOR, IOG, IOB, I
SYNC )
DIGITAL INPUTS
(R0-R7, G0-G7, B0-B7;
SYNC, BLANK,
REF WHITE)
DATA
Figure 2. Video Data Input/Output
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