參數(shù)資料
型號: ADV476KN66
廠商: ANALOG DEVICES INC
元件分類: 顯示控制器
英文描述: CMOS Monolithic 256x18 Color Palette RAM-DAC
中文描述: PALETTE-DAC DSPL CTLR, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 3/12頁
文件大?。?/td> 175K
代理商: ADV476KN66
ADV476
REV. B
–3–
TIMNGCHARACTERISTICS
1
Parameter
66 MHz Version
50 MHz Version
35 MHz Version
Units
Conditions/Comments
f
MAX
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
66
10
10
5
40
20
10
10
50
4
3
t
12
3
3
15.3
5
5
30
5
6
15.3
2
4
50
10
10
5
40
20
10
10
50
4
3
t
12
3
3
20
6
6
30
5
8
20
2
4
35
15
15
5
40
20
15
15
50
4
3
t
12
4
4
28
7
9
30
5
8
25
2
4
MHz
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns typ
ns min
clocks
Clock Rate
RS0, RS1 Setup T ime
RS0, RS1 Hold T ime
RD
Asserted to Data Bus Driven
RD
Asserted to Data Valid
RD
Negated to Data Bus 3-Stated
Write Data Setup T ime
Write Data Hold T ime
RD
,
WR
Pulse Width Low
RD
,
WR
Pulse Width High
Pixel & Control Setup T ime
Pixel & Control Hold T ime
Clock Cycle T ime
Clock Pulse Width High T ime
Clock Pulse Width Low T ime
Analog Output Delay
t
t
16
t
18
t
PD
Analog Output Rise/Fall T ime
Analog Output Settling T ime
Analog Output Skew
Pipeline Delay
NOT ES
1
T T L input values are 0 to 3 volts, with input rise/fall times
3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and
outputs. Analog output load
10 pF, 37.5
. D0–D7 output load
50 pF. See timing notes in Figure 2.
2
T emperature Range (T
MIN
to T
MAX
); 0 to +70
°
C
3
Settling time does not include clock and data feedthrough. For this test, the digital inputs have a 1 k
resistor to ground and are driven by 74HC logic.
Specifications subject to change without notice.
Figure 1. MPU Read/Write Timing
Figure 2. Video Input/Output Timing
(V
CC
= +5 V
6
10%. All Specifications T
MN
to T
MAX2
)
相關(guān)PDF資料
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