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參數(shù)資料
| 型號： | ADV476KN50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | Circular Connector; No. of Contacts:66; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:19; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:19-35 |
| 中文描述： | PALETTE-DAC DSPL CTLR, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 175K |
| 代理商： | ADV476KN50 |
ADV476
REV. B
–6–
MPU Interface
As illustrated in the functional block diagram, the ADV476 sup-
ports a standard MPU bus interface, allowing the MPU direct
access to the color palette RAM.
T he RS0 and RS1 control inputs specify whether the MPU is
accessing the address register or the color palette RAM, as
shown in T able I. T he 8-bit address register is used to address
the color palette RAM, eliminating the requirement for external
address multiplexers.
T able I. Control Input T ruth T able
RS1
RS0
Addressed by MPU
0
1
0
1
0
1
1
0
Pixel Address Register (RAM Write Mode)
Pixel Address Register (RAM Read Mode)
Color Palette RAM
Pixel Read Mask Register
T o write color data, the MPU writes to the address register with
the 8-bit address of the color palette RAM location which is to
be modified. T he MPU performs three successive write cycles
(six bits of red data, six bits of green data and six bits of blue
data). During the blue write cycle, the three bytes of color infor-
mation are concatenated into an 18-bit word and written to the
then automatically increments to the next location which the
MPU may modify by simply writing another sequence of red,
green and blue data.
T o read back color data, the MPU loads the address register
with the address of the color palette RAM location to be read.
T he MPU performs three successive read cycles (6 bits each of
red, green and blue data). Following the blue read cycle, the
address register increments to the next location which the MPU
may read by simply reading another sequence of red, green and
blue data.
T his 6-bit color data is right justified, i.e., the lower six bits of
the data bus with D0 being the LSB and D5 the MSB. D6 and
D7 are ignored during a color write cycle and are set to zero
during a color read cycle.
During color palette RAM access, the address register resets to
00H following a blue read or write operation to RAM location
FFH.
T he MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM and the color
registers (R, G, and B in the block diagram) are synchronized by
internal logic, and occur in the period between MPU accesses.
Color (RGB) data is normally loaded to the color palette RAM
during video screen retrace, i.e., during the video waveform
blanking period, see Figure 5.
T o keep track of the red, green and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in T able II. T hey are reset to
zero when the MPU writes to the address register, and are not
reset to zero when the MPU reads the address register. T he
MPU does not have access to these bits. T he other eight bits of
the address register, incremented following a blue read or write
cycle, (ADDR0–7) are accessible to the MPU, and are used to
address color palette RAM locations, as shown in T able III.
ADDR0 is the LSB when the MPU is accessing the RAM. T he
MPU may read the address register at any time without modify-
ing its contents or the existing read/write mode.
Figure 1 illustrates the MPU read/write timing and T able III
shows the associated functional instructions.
T able II. Address Register (ADDR) Operation
Value
RS1
RS0
Addressed by MPU
ADDRa,b (Counts Modulo 3)
00
01
10
Red Value
Green Value
Blue Value
ADDR0–7 (Counts Binary)
00H–FFH
0
1
Color Palette RAM
T able III. T ruth T able for Read/Write Operations
RD
WR
RS0
RS1
ADDRa
ADDRb
Operation Performed
1
0
0
0
X
X
Write Address Register;
D0–D7
→
ADDR0–7
0
→
ADDRa,b
Increment ADDRa–b
Increment ADDRa–b
Modify RAM Location
Increment ADDR0–7
Increment ADDRa–b
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
Write Red Value;
Write Green Value;
Write Blue Value;
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
X
0
0
1
X
0
1
0
Read Address Register;
Read Red Value;
Read Green Value;
Read Blue Value;
ADDR0–7
→
D0–D7
Increment ADDRa–b
Increment ADDRa–b
Increment ADDR0–7
Increment ADDRa–b
0
0
X
X
X
X
Invalid Operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV478 | CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs |
| ADV471KP35 | Circular Connector; No. of Contacts:37; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:15-35 |
| ADV471KP50 | CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs |
| ADV471KP66 | Circular Connector; No. of Contacts:37; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle |
| ADV471KP80 | Circular Connector; No. of Contacts:37; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV476KN50E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADV476KN66 | 制造商:Analog Devices 功能描述: |
| ADV476KN70 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADV476KN80 | 制造商:Analog Devices 功能描述: |
| ADV476KN80E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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