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參數(shù)資料
| 型號： | ADV3200ASWZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 32X32 176LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 32:32 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 5V，±2.5V，±3.3V |
| 電流 - 電源： | 250mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP |
| 供應(yīng)商設(shè)備封裝： | 176-LQFP-EP（24x24） |
| 包裝： | 托盤 |
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ADV3200/ADV3201
Rev. 0 | Page 27 of
36
THEORY OF OPERATION
The ADV3200/ADV3201 are single-ended crosspoint arrays
with 32 outputs, each of which can be connected to any one
of 32 inputs. Thirty-two switchable input stages are connected
to each output buffer to form 32-to-1 multiplexers. There are 32
of these multiplexers, each with its inputs wired in parallel, for a
total array of 1024 stages forming a multicast-capable crosspoint
switch (see Figure 97).
In addition to connecting to any of the nominal inputs (INxx),
each output can also be connected to an associated OSDxx input
through an additional 2-to-1 multiplexer at each output. This
2-to-1 multiplexer switches between the output of the 32-to-1
multiplexer and the OSDxx input.
x1
OUT00
VPOS
VNEG
FROM INPUT
STAGES
VPOS
VNEG
OSD00
OSDS00
07
17
6-
00
6
Figure 95. Conceptual Diagram of Single Output Channel, G = +1 (ADV3200)
Decoding logic for each output selects one (or none) of the
input stages to drive the output stage. The enabled input stage
drives the output stage, which is configured as a unity-gain
amplifier in the ADV3200 (see Figure 95).
In the ADV3201, an internal resistive feedback network and
reference buffer provide for a total output stage gain of +2 (see
Figure 96). The input voltage to the reference buffer is the
VREF pin. This voltage is common to the entire chip and needs
to be driven from a low impedance source to avoid crosstalk.
OUT00
x1
VPOS
VNEG
FROM INPUT
STAGES
VPOS
VNEG
VREF
VPOS
VNEG
OSD00
OSDS00
2k
07
17
6-
0
07
Figure 96. Conceptual Diagram of Single Output Channel, G = +2 (ADV3201)
Each input to the ADV3200/ADV3201 is buffered by a receiver.
This receiver provides overvoltage protection for the input
stages by limiting signal swing. In the ADV3200, the output
of the receiver is limited to ±1.2 V about VREF, whereas in the
ADV3201, the signal swing is limited to ±1.2 V about midsupply.
This receiver is configured as a voltage feedback unity-gain
amplifier. Excess loop gain bandwidth product reduces the
effect of the closed-loop gain on the bandwidth of the device.
SWITCH
MATRIX
SYNC-TIP
CLAMP
RECEIVER
INxx
GND
OPTIONAL
AC COUPLING
CAPACITOR
75
OUTxx 75
75
ADV3200/ADV3201
VREF
OSDxx
OSDSxx
VCLAMP
BYPASS SYNC-TIP
CLAMP
07
17
6-
11
0
OUTPUT
BUFFER
G = +1 (ADV3200)
G = +2 (ADV3201)
Figure 97. ADV3200/ADV3201 Signal Chain (Single I/O Path)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV3200-EVALZ | 功能描述:ADV3200 - Interface, Crosspoint Switch/Multiplexer Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:接口，交叉點(diǎn)開關(guān)/多路復(fù)用器 嵌入式:- 使用的 IC/零件:ADV3200 主要屬性:32 x 32 視頻交叉點(diǎn)開關(guān) 輔助屬性:圖形用戶界面 所含物品:板，線纜 標(biāo)準(zhǔn)包裝:1 |
| ADV3201 | 制造商:AD 制造商全稱:Analog Devices 功能描述:300 MHz, 32 × 32 Buffered Analog Crosspoint Switch |
| ADV3201ASWZ | 功能描述:IC CROSSPOINT SWIT 32X32 176LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 功能:開關(guān) 電路:單刀單擲 導(dǎo)通狀態(tài)電阻:48 歐姆 電壓電源:單電源 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電流 - 電源:5µA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:托盤 |
| ADV3201-EVALZ | 功能描述:ADV3201 - Interface, Crosspoint Switch/Multiplexer Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:接口，交叉點(diǎn)開關(guān)/多路復(fù)用器 嵌入式:- 使用的 IC/零件:ADV3201 主要屬性:32 x 32 視頻交叉點(diǎn)開關(guān) 輔助屬性:圖形用戶界面 所含物品:板，線纜 標(biāo)準(zhǔn)包裝:1 |
| ADV3202 | 制造商:AD 制造商全稱:Analog Devices 功能描述:300 MHz, 32 × 16 Buffered Analog Crosspoint Switch |
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