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參數(shù)資料
| 型號(hào)： | ADV101KP80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Circular Connector; No. of Contacts:3; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:9; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:9-98 |
| 中文描述： | TRIPLE, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 187K |
| 代理商： | ADV101KP80 |
ADV101
–9–
REV. B
T he unused analog outputs should be terminated with the same
load as that for the used channel. In other words, if the red
channel is used and IOR is terminated with a doubly termi-
nated 75
load (37.5
), IOB and IOG should be terminated
with 37.5
resistors. (See Figure 6.)
GND
ADV101
R0
R7
G0
G7
B0
B7
VIDEO
INPUT
DOUBLY
TERMINATED
75
LOAD
IOR
IOG
IOB
37.5
37.5
Figure 6. Input and Output Connections for Stand-Alone
Gray Scale or Composite Video
Video Output Buffers
T he ADV101 is specified to drive transmission line loads, which
is what most monitors are rated as. T he analog output configu-
rations to drive such loads are described in the Analog Interface
section and illustrated in Figure 5. However, in some applica-
tions it may be required to drive long “transmission line” cable
lengths. Cable lengths greater than 10 meters can attenuate and
distort high frequency analog output pulses. T he inclusion of
output buffers will compensate for some cable distortion. Buff-
ers with large full power bandwidths and gains between 2 and 4
will be required. T hese buffers will also need to be able to sup-
ply sufficient current over the complete output voltage swing.
Analog Devices produces a range of suitable op amps for such
applications. T hese include the AD84X series of monolithic op
amps. In very high frequency applications (80 MHz), the
AD9617 is recommended. More information on line driver buff-
ering circuits is given in the relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit will result in any desired video
level.
DACs
Z = 75
(CABLE)
Z = 75
S
(SOURCE
TERMINATION)
AD848
V
S
–
V
S
+
0.1
μ
F
0.1
μ
F
IOR, IOG, IOB
75
2
7
6
4
3
Z
2
Z
1
Z = 75
(MONITOR)
GAIN (G) = 1 +Z
1
Z
2
Figure 7. AD848 As an Output Buffer
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