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參數(shù)資料
| 型號： | ADUM5242 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual-Channel Isolators with Integrated DC/DC Converter, 50 mW |
| 中文描述： | 雙通道隔離器的集成DC / DC轉(zhuǎn)換器，50毫瓦 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 152K |
| 代理商： | ADUM5242 |
Preliminary Technical Data
ADuM5240/ADuM5241/ADuM5242
Parameter
AC SPECIFICATIONS
Minimum Pulse Width
5
Maximum Data Rate
6
Propagation Delay
7
Pulse-Width Distortion, |t
PLH
t
PHL
|
7
Propagation Delay Skew
8
Channel-to-Channel Matching,
Codirectional Channels
9
Channel-to-Channel Matching,
Opposing-Directional Channels
10
Ripple
11
Enable Time
12
Disable Time
12
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
Refresh Frequency
Rev. PrN | Page 3 of 10
Symbol
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
Min
10
25
Typ
Max
100
70
3
45
3
Unit
ns
Mbps
ns
ns
ns
ns
Test Conditions
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
t
PSKCD
15
ns
C
L
= 15 pF, CMOS signal levels
T
ENABLE
T
DISABLE
t
R
/t
F
|CM
H
|
25
200
50
50
2.5
35
mV
P-P
ns
ns
ns
kV/μs
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD
, V
ISO
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V = 1000 V,
transient magnitude = 800 V
|CM
L
|
25
35
kV/μs
f
r
1.0
MHz
1
All voltages are relative to their respective ground.
2
Supply current values are specified with no load present on the digital outputs.
3
Supply current values are specified with no load present on the digital outputs.
4
Enable/disable threshold is the voltage at which the internal DC/DC converter is enabled/disabled.
5
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
6
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
7
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
8
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
9
Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
10
Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
11
Ripple occurs at frequency corresponding to the input signal data rate or the refresh frequency for data rates below 1Mbps.
12
Enable time is the duration from when input supply voltage rises above the enable threshold to when the internal DC/DC converter starts charging an external load.
Disable time is the duration from when the input supply voltage drops below the disable threshold to when the internal DC/DC converter stops charging an external
load
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input-Output)
Capacitance (Input-Output)
Input Capacitance
IC Junction-to-Air Thermal Resistance
Symbol
R
I-O
C
I-O
C
I
θ
JA
Min
Typ
10
12
1.0
4.0
150
Max
Unit
Ω
pF
pF
°C/W
Test Conditions
f = 1 MHz
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