參數(shù)資料
型號(hào)： ADUM1250ARZ-RL7
廠商： ANALOG DEVICES INC
元件分類： 其它接口
英文描述： Hot Swappable Dual I2C Isolators
中文描述： SPECIALTY INTERFACE CIRCUIT, PDSO8
封裝： ROHS COMPLIANT, MS-012AA, SOIC-8
文件頁數(shù)： 4/12頁
文件大小： 201K
代理商： ADUM1250ARZ-RL7
ADuM1250/ADuM1251
AC Specifications
All voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= 5 V, and V
DD2
= 5 V, unless otherwise noted. Refer to Figure 5.
Rev. 0 | Page 4 of 12
Table 2.
Parameter
MAXIMUM FREQUENCY
OUTPUT FALL TIME
5 V Operation
Symbol
Min
1000
Typ
Max
Unit
kHz
Test Conditions
4.5 V ≤ V
DD1
,V
DD2
≤ 5.5 V, C
L1
= 40 pF, R1 = 1.6 kΩ,
C
L2
= 400 pF, R2 = 180 Ω
3.0 V ≤ V
DD1
,V
DD2
≤ 3.6 V, C
L1
= 40 pF, R1 = 1.0 kΩ,
C
L2
= 400 pF, R2 = 120 Ω
4.5 ≤ V
DD1
, V
DD2
≤ 5.5 V,
C
L1
= C
L2
= 0, R1 = 1.6 kΩ, R2 = 180 Ω
3.0 V ≤ V
DD1
,V
DD2
≤ 3.6 V,
C
L1
= C
L2
= 0, R1 = 1.0 kΩ, R2 = 120 Ω
4.5 V ≤ V
DD1
, V
DD2
≤ 5.5 V,
C
L1
= C
L2
= 0, R1 = 1.6 kΩ, R2 = 180 Ω
3.0 V ≤ V
DD1
,V
DD2
≤ 3.6 V,
C
L1
= C
L2
= 0, R1 = 1.0 kΩ, R2 = 120 Ω
Side 1 Output (0.9 V
DD1
to 0.9 V)
Side 2 Output (0.9 V
DD2
to 0.1 V
DD2
)
3 V Operation
t
f1
t
f2
13
32
26
52
120
120
ns
ns
Side 1 Output (0.9 V
DD1
to 0.9 V)
Side 2 Output (0.9 V
DD2
to 0.1 V
DD2
)
PROPAGATION DELAY
5 V Operation
t
f1
t
f2
13
32
32
61
120
120
ns
ns
Side 1-to-Side 2, Rising Edge
1
Side 1-to-Side 2, Falling Edge
2
Side 2-to-Side 1, Rising Edge
3
Side 2-to-Side 1, Falling Edge
4
3 V Operation
t
PLH12
t
PHL12
t
PLH21
t
PHL21
95
162
31
85
130
275
70
155
ns
ns
ns
ns
Side 1-to-Side 2, Rising Edge
1
Side 1-to-Side 2, Falling Edge
2
Side 2-to-Side 1, Rising Edge
3
Side 2-to-Side 1, Falling Edge
4
PULSE WIDTH DISTORTION
5 V Operation
t
PLH12
t
PHL12
t
PLH21
t
PHL21
82
196
32
110
125
340
75
210
ns
ns
ns
ns
Side 1-to-Side 2, |t
PLH12
t
PHL12
|
Side 2-to-Side 1, |t
PLH21
t
PHL21
|
3 V Operation
PWD
12
PWD
21
67
54
145
85
ns
ns
Side 1-to-Side 2, |t
PLH12
t
PHL12
|
Side 2-to-Side 1, |t
PLH21
t
PHL21
|
COMMON-MODE TRANSIENT
IMMUNITY
5
1
t
PLH12
propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 V
DD2
.
2
t
PHL12
propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V.
3
t
PLH21
propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 V
DD1
.
4
t
PLH21
propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V.
5
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
PWD
12
PWD
21
|CM
H
|,
|CM
L
|
25
114
77
35
215
135
ns
ns
kV/μs
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