參數(shù)資料
型號: ADUC846BCP32-5
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU
中文描述: 16-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封裝: 8 X 8 MM, LFCSP-56
文件頁數(shù): 17/20頁
文件大?。?/td> 1984K
代理商: ADUC846BCP32-5
ADuC846
REV. PrA
-17-
PRELIMINARY TECHNICAL DATA
8052 Instruction Set
The following pages document the number of clock cycles required
for each instruction. Most instructions are executed in one or two
clock cycles resulting in 12.6MIPs peak performance when
operating at PLLCON = 00H.
Timer Operation
Timers on a standard 8052 increment by one with each machine
cycle. On the ADuC846 one machine cycle is equal to one clock
cycle hence the timers will increment at the same rate as the core
clock.
ALE
The output on the ALE pin on the ADuC836 was a clock at 1/6th of
the core operating frequency. On the ADuC846 the ALE pin
operates as follows.
For a single machine cycle instruction: ALE is high for the first
half of the machine cycle and low for the second half. The ALE
output is at the core operating frequency.For a two or more
machine cycle instruction: ALE is high for the first half of the first
machine cycle and then low for the rest of the machine cycles.
External Memory Access
There is no support for external program memory access on the
ADuC846. When accessing external RAM the EWAIT register
may need to be programmed in order to give extra machine cycles
to MOVX commands. This is to account for differing external
RAM access speeds.
INSTRUCTION TABLE
TABLE IV: Optimized Single Cycle 8051 Instruction Set
Description
Add register to A
Add indirect memory to A
Add register to A with carry
Add indirect memory to A with carry
Add direct byte to A
Add direct byte to A with carry
Subtract register from A with borrow
Subtract indirect memory from A with borrow
Subtract direct from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment indirect memory
Increment direct byte
Increment data pointer
Decrement A
Decrement Register
Decrement indirect memory
Decrement direct byte
Multiply A by B
Divide A by B
Decimal Adjust A
Mnemonic Arithmetic
ARITHMETIC
ADD A,Rn
ADD A,@Ri
ADDC A,Rn
ADDC A,@Ri
ADD A,dir
ADD A,#data
SUBB A,Rn
SUBB A,@Ri
SUBB A,dir
SUBB A,#data
INC A
INC Rn
INC @Ri
INC dir
INC DPTR
DEC A
DEC Rn
DEC @Ri
DEC dir
MUL AB
DIV AB
DA A
Bytes
1
1
1
1
2
2
1
1
2
1
1
1
1
2
1
1
1
1
2
1
1
1
Cycles
1
2
1
2
2
2
1
2
2
1
1
1
2
2
3
1
1
2
2
9
9
2
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