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參數(shù)資料
| 型號(hào)： | ADUC846 |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | ADC |
| 英文描述： | MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU |
| 中文描述： | MicroConverter的，雙16的嵌入式62kB閃存MCU位ADC |
| 文件頁(yè)數(shù)： | 15/20頁(yè) |
| 文件大小： | 1984K |
| 代理商： | ADUC846 |
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ADuC846
REV. PrA
-15-
PRELIMINARY TECHNICAL DATA
EXSP (CFG846.7) bit must be set otherwise the SPH SFR cannot be
read or written to.
Program Status Word (PSW)
The PSW SFR contains several bits reflecting the current status of the
CPU as detailed in Table I.
SFR Address
Power ON Default Value
Bit Addressable
Table I. PSW SFR Bit Designations
Bit Name
Description
7
CY
Carry Flag
6
AC
Auxiliary Carry Flag
5
F0
General-Purpose Flag
4
RS1
Register Bank Select Bits
3
RS0
RS1
RS0
Selected Bank
0
0
0
0
1
1
1
0
2
1
1
3
2
OV
Overflow Flag
1
F1
General-Purpose Flag
0
P
Parity Bit
The PCON SFR contains bits for power-saving options and general-
purpose status flags as shown in Table II.
SFR Address
Power ON Default Value
Bit Addressable
Table II. PCON SFR Bit Designations
Bit Name
Description
7
SMOD
Double UART Baud Rate
6
SERIPD
SPI Power-Down Interrupt Enable
5
INT0PD
INT0 Power-Down Interrupt Enable
4
ALEOFF Disable ALE Output
3
GF1
General-Purpose Flag Bit
2
GF0
General-Purpose Flag Bit
1
PD
Power-Down Mode Enable
0
IDL
Idle Mode Enable
D0H
00H
Yes
87H
00H
No
The CFG846 SFR contains the necessary bits to configure the
internal XRAM and the extended SP. By default it configures the
user into 8051 mode. i.e. extended SP is disabled, internal XRAM is
disabled.
SFR Address
Power ON Default Value
Bit Addressable
Table III. CFG846 SFR Bit Designations
Bit Name
Description
7
EXSP
Extended SP Enable
If this bit is set then the stack will
rollover from SPH/SP = 00FFh to
0100h.
If this bit is clear then the SPH SFR will be
disabled and the stack will rollover from SP=FFh to
SP = 00h
6
----
----
5
----
----
4
----
----
3
----
----
2
----
----
1
----
----
0
XRAMEN XRAM Enable Bit
If this bit is set then the internal
XRAM will be mapped into the lower
2kBytes of the external address space.
If this bit is clear then the internal
XRAM will not be accessible and the
external data memory will be mapped
into the lower 2kBytes of external data
memory. (see figure 3)
AFhH
00H
No
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