參數(shù)資料
型號(hào): ADUC843BS62-3
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
中文描述: 8-BIT, FLASH, 8.38 MHz, MICROCONTROLLER, PQFP52
封裝: PLASTIC, MO-112AC1, MQFP-52
文件頁數(shù): 49/88頁
文件大小: 903K
代理商: ADUC843BS62-3
ADuC841/ADuC842/ADuC843
Bit No.
2
Rev. 0 | Page 49 of 88
Name
I2CRS
Description
I
2
C Reset Bit (Slave Mode Only).
Set by the user to reset the I
2
C interface.
Cleared by the user code for normal I
2
C operation.
I
2
C Direction Transfer Bit (Slave Mode Only).
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
I
2
C Interrupt Bit (Slave Mode Only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below).
1
I2CTX
0
I2CI
I2CADD
Function
I
2
C Address Register
Holds the first I
2
C peripheral address for the part. It may be overwritten by user code. Application Note
uC001 at www.analog.com/microconverter describes the format of the I
2
C standard 7-bit address in
detail.
9BH
55H
No
I
2
C Address Register
Holds the second I
2
C peripheral address for the part. It may be overwritten by user code.
91H
7FH
No
I
2
C Address Register
Holds the third I
2
C peripheral address for the part. It may be overwritten by user code.
92H
7FH
No
I
2
C Address Register
Holds the fourth I
2
C peripheral address for the part. It may be overwritten by user code.
93H
7FH
No
I
2
C Data Register
Written by the user to transmit data over the I
2
C interface or read by user code to read data just
received by the I
2
C interface. Accessing I2CDAT automatically clears any pending I
2
C interrupt and
the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle.
9AH
00H
No
The main features of the MicroConverter I
2
C interface are
Only two bus lines are required: a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I
2
C master can communicate with multiple slave
devices. Because each slave device has a unique 7-bit
SFR Address
Power-On Default
Bit Addressable
I2CADD1
Function
SFR Address
Power-On Default
Bit Addressable
I2CADD2
Function
SFR Address
Power-On Default
Bit Addressable
I2CADD3
Function
SFR Address
Power-On Default
Bit Addressable
I2CDAT
Function
SFR Address
Power-On Default
Bit Addressable
address, single master/slave relationships can exist at all
times even in a multislave environment.
Ability to respond to four separate addresses when
operating in slave mode.
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