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參數(shù)資料
| 型號(hào)： | ADUC842BCP32-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FRAME, MO-220VLLD2, CSP-56 |
| 文件頁數(shù)： | 78/88頁 |
| 文件大?。?/td> | 903K |
| 代理商： | ADUC842BCP32-5 |
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ADuC841/ADuC842/ADuC843
TIMING SPECIFICATIONS
1, 2, 3
Table 41. AV
DD
=2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications T
MIN
to T
MAX
,
unless otherwise noted
Parameter
ADuC842/ADuC843 CLOCK INPUT
(External Clock Driven XTAL1)
t
CK
XTAL1 Period
t
CKL
XTAL1 Width Low
t
CKH
XTAL1 Width High
t
CKR
XTAL1 Rise Time
t
CKF
XTAL1 Fall Time
1/t
CORE
ADuC842/ADuC843 Core Clock Frequency
4
t
CORE
ADuC842/ADuC843 Core Clock Period
5
t
CYC
ADuC842/ADuC843 Machine Cycle Time
6
Rev. 0 | Page 78 of 88
32.768 kHz External Crystal
Typ
30.52
6.26
6.26
9
9
0.476
0.476
Unit
μs
μs
μs
ns
ns
MHz
μs
μs
Min
0.131
0.059
Max
16.78
7.63
1
AC inputs during testing are driven at DV
DD
– 0.5 V for a Logic 1 and 0.45 V for Logic 0. Timing measurements are made at V
IH
min for Logic 1 and V
IL
max for Logic 0, as
shown in Figure 87.
2
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded V
OH
/V
OL
level occurs, as shown in Figure 87.
3
C
LOAD
for all outputs = 80 pF, unless otherwise noted.
4
ADuC842/ADuC843 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 16.78 MHz internal clock for the
system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
5
This number is measured at the default Core_Clk operating frequency of 2.09 MHz.
6
ADuC842/ADuC843 machine cycle time is nominally defined as 1/Core_CLK.
Parameter
ADuC841 CLOCK INPUT
(External Clock Driven XTAL1)
t
CK
XTAL1 Period
t
CKL
XTAL1 Width Low
t
CKH
XTAL1 Width High
t
CKR
XTAL1 Rise Time
t
CKF
XTAL1 Fall Time
1/t
CORE
ADuC841 Core Clock Frequency
t
CORE
ADuC841 Core Clock Period
t
CYC
ADuC841 Machine Cycle Time
Variable External Crystal
Typ
0.476
0.476
Unit
ns
ns
ns
ns
ns
MHz
μs
μs
Min
62.5
20
20
0.131
0.05
Max
1000
20
20
20
7.63
t
CKH
t
CKL
t
CK
t
CKF
t
CKR
0
Figure 86. XTAL1 Input
DV
DD
– 0.5V
0.45V
0.2DV
+ 0.9V
TEST POINTS
0.2DV
DD
– 0.1V
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINTS
V
LOAD
– 0.1V
V
LOAD
V
LOAD
– 0.1V
0
Figure 87. Timing Waveform Characteristics
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