參數(shù)資料
型號: ADUC841BSZ62-3
廠商: Analog Devices Inc
文件頁數(shù): 51/88頁
文件大?。?/td> 0K
描述: IC ADC/DAC 12BIT W/MCU 52-MQFP
產(chǎn)品培訓模塊: Process Control
標準包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 8.38MHz
連通性: I²C,SPI,UART/USART
外圍設備: DMA,PSM,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 62KB(62K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 52-QFP
包裝: 托盤
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
配用: EVAL-ADUC841QSZ-ND - KIT DEV FOR ADUC841 QUICK START
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 55 of 88
Table 24. TIMECON SFR Bit Designations
Bit No.
Name
Description
7
----
Reserved.
6
TFH
Twenty-Four Hour Select Bit.
Set by the user to enable the hour counter to count from 0 to 23.
Cleared by the user to enable the hour counter to count from 0 to 255.
5
ITS1
Interval Timebase Selection Bits.
4
ITS0
Written by user to determine the interval counter update rate.
ITS1
ITS0
Interval Timebase
0
1/128 Second
0
1
Seconds
1
0
Minutes
1
Hours
3
STI
Single Time Interval Bit.
Set by the user to generate a single interval timeout. If set, a timeout clears the TIEN bit.
Cleared by the user to allow the interval counter to be automatically reloaded and start counting again at each
interval timeout.
2
TII
TIC Interrupt Bit.
Set when the 8-bit interval counter matches the value in the INTVAL SFR.
Cleared by user software.
1
TIEN
Time Interval Enable Bit.
Set by the user to enable the 8-bit time interval counter.
Cleared by the user to disable the interval counter.
0
TCEN
Time Clock Enable Bit.
Set by the user to enable the time clock to the time interval counters.
Cleared by the user to disable the clock to the time interval counters and reset the time interval SFRs to the last
value written to them by the user. The time registers (HTHSEC, SEC, MIN, and HOUR) can be written while TCEN
is low.
TIMECON
TIC Control Register
SFR Address
A1H
Power-On Default
00H
Bit Addressable
No
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