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參數(shù)資料
| 型號(hào)： | ADUC841BCP8-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Cable Gland (Clamp); Connector Shell Size:14, 14S; Thread Size:3/4-20; Body Material:Zinc Alloy |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FRAME, MO-220VLLD2, CSP-56 |
| 文件頁數(shù)： | 53/88頁 |
| 文件大?。?/td> | 903K |
| 代理商： | ADUC841BCP8-5 |
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ADuC841/ADuC842/ADuC843
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
or interrupt within a reasonable amount of time if the ADuC841/
ADuC842/ADuC843 enter an erroneous state, possibly due to a
programming error or electrical noise. The watchdog function
can be disabled by clearing the WDE (watchdog enable) bit in
the watchdog control (WDCON) SFR. When enabled, the
watchdog circuit generates a system reset or interrupt (WDS) if
the user program fails to set the watchdog (WDE) bit within a
predetermined amount of time (see PRE3-0 bits in Table 23.
The watchdog timer is clocked directly from the 32 kHz
external crystal on the ADuC842/ADuC843. On the ADuC841,
Table 23. WDCON SFR Bit Designations
Bit No.
Name
Description
7
PRE3
Watchdog Timer Prescale Bits.
6
PRE2
The watchdog timeout period is given by the equation
t
WD
= (2
PRE
× (2
9
/ f
XTAL
))
5
PRE1
(0 – PRE – 7; f
XTAL
= 32.768 kHz (ADuC842/ADuC843), or 32kHz ± 10%(ADuC841) )
PRE3
PRE2
PRE1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
PRE3–0 > 1000
3
WDIR
Watchdog Interrupt Response Enable Bit.
If this bit is set by the user, the watchdog generates an interrupt response instead of a system reset when the
watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction, and it is also a fixed,
high priority interrupt. If the watchdog is not being used to monitor the system, it can be used alternatively as a
timer. The prescaler is used to set the timeout period in which an interrupt will be generated.
2
WDS
Watchdog Status Bit.
Set by the watchdog controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
1
WDE
Watchdog Enable Bit.
Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within the watchdog
timeout period, the watchdog generates a reset or interrupt, depending on WDIR.
Cleared under the following conditions: user writes 0, watchdog reset (WDIR = 0); hardware reset; PSM interrupt.
Watchdog Write Enable Bit.
To write data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the very
next instruction must be a write instruction to the WDCON SFR.
For example:
CLR
EA
;disable interrupts while writing
;to WDT
SETB
WDWR
;allow write to WDCON
MOV
WDCON,#72H
;enable WDT for 2.0s timeout
SETB
EA
;enable interrupts again (if rqd)
Rev. 0 | Page 53 of 88
the watchdog timer is clocked by an internal R/C oscillator at
32 kHz ±10%. The WDCON SFR can be written only by user
software if the double write sequence described in WDWR
below is initiated on every write access to the WDCON SFR.
WDCON Watchdog Timer
SFR Address
Power-On Default
Bit Addressable
Control Register
C0H
10H
Yes
PRE0
0
1
0
1
0
1
0
1
0
Timeout Period (ms)
15.6
31.2
62.5
125
250
500
1000
2000
0.0
Action
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Immediate Reset
Reserved
4
PRE0
0
WDWR
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