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| 型號： | ADUC824BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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REV. B
ADuC824
–19–
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Type
*
Description
1
P1.0/T2
I/O
Port 1.0 can function as a digital input or digital output and has a pull-up configuration as
described below for Port 3. P1.0 has an increased current drive sink capability of 10 mA and can
also be used to provide a clock input to Timer 2. When Enabled, Counter 2 is incremented in
response to a negative transition on the T2 input pin.
2
P1.1/T2EX
I/O
Port 1.1 can function as a digital input or digital output and has a pull-up configuration as
described below for Port 3. P1.1 has an increased current drive sink capability of 10 mA and
can also be used to provide a control input to Timer 2. When Enabled, a negative transition on
the T2EX input pin will cause a Timer 2 capture or reload event.
3
P1.2/DAC/IEXC1 I/O
Port 1.2. This pin has no digital output driver; it can function as a digital input for which ‘0’
must be written to the port bit. As a digital input, P1.2 must be driven high or low externally.
The voltage output from the DAC can also be configured to appear at this pin. If the DAC
output is not being used, one or both of the excitation current sources (200
A or 2 × 200 A)
can be programmed to be sourced at this pin.
4
P1.3/AIN5/IEXC2 I
Port 1.3. This pin has no digital output driver; it can function as a digital input for which ‘0’ must
be written to the port bit. As a digital input, P1.3 must be driven high or low externally. This
pin can provide an analog input (AIN5) to the auxiliary ADC and one or both of the excitation
current sources (200
A or 2 × 200 A) can be programmed to be sourced at this pin.
5AVDD
S
Analog Supply Voltage, 3 V or 5 V
6
AGND
S
Analog Ground. Ground reference pin for the analog circuitry
7
REFIN(–)
I
Reference Input, Negative Terminal
8
REFIN(+)
I
Reference Input, Positive Terminal
9–11
P1.4–P1.6
I
Port 1.4 to P1.6. These pins have no digital output drivers; they can function as digital inputs,
for which ‘0’ must be written to the respective port bit. As a digital input, these pins must be
driven high or low externally. These port pins also have the following analog functionality:
P1.4/AIN1
I
Primary ADC Channel, Positive Analog Input
P1.5/AIN2
I
Primary ADC Channel, Negative Analog Input
P1.6/AIN3
I
Auxiliary ADC Input or muxed Primary ADC Channel, Positive Analog Input
12
P1.7/AIN4/DAC I/O
Port 1.7. This pin has no digital output driver; it can function as a digital input for which ‘0’ must be
written to the port bit. As a digital input, P1.7 must be driven high or low externally. This pin can
provide an analog input (AIN4) to the auxiliary ADC or muxed Primary ADC Channel, Negative
Analog Input. The voltage output from the DAC can also be configured to appear at this pin.
13
SS
I
Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.
14
MISO
I/O
Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this input pin.
15
RESET
I
Reset Input. A high level on this pin for 24 core clock cycles while the oscillator is running resets
the device. There is a weak pull-down and a Schmitt trigger input stage on this pin. External
POR (power-on reset) circuitry must be added to drive the RESET pin as described later in
this data sheet.
16–19
P3.0–P3.3
I/O
P3.0–P3.3 are bidirectional port pins with internal pull-up resistors. Port 3 pins that have 1s written
to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs.
As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up
resistors. When driving a 0-to-1 output transition, a strong pull-up is active for two core clock
periods of the instruction cycle. Port 3 pins also have various secondary functions described below.
P3.0/RXD
I/O
Receiver Data Input (asynchronous) or Data Input/Output (synchronous) of serial (UART) port.
P3.1/TXD
I/O
Transmitter Data Output (asynchronous) or Clock Output (synchronous) of serial (UART) port.
P3.2/
INT0
I/O
Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed
to one of two priority levels. This pin can also be used as a gate control input to Timer0.
P3.3/
INT1
I/O
Interrupt 1, programmable edge-or level-triggered Interrupt input, which can be programmed
to one of two priority levels. This pin can also be used as a gate control input to Timer1.
20, 34, 48
DVDD
S
Digital supply, 3 V or 5 V
21, 35, 47
DGND
S
Digital ground, ground reference point for the digital circuitry
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