參數(shù)資料
型號: ADUC816BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 36/68頁
文件大小: 0K
描述: IC MCU FLASH 16BIT ADC 56LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 12.58MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: PSM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 7x16b; D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 托盤
REV. 0
ADuC816
–41–
USER INTERFACE TO OTHER ON-CHIP ADuC816
PERIPHERALS
The following section gives a brief overview of the various
peripherals also available on-chip. A summary of the SFRs used
to control and configure these peripherals is also given.
DAC
The ADuC816 incorporates a 12-bit, voltage output DAC
on-chip. It has a rail-to-rail voltage output buffer capable of
driving 10 k
Ω/100 pF. It has two selectable ranges, 0 V to V
REF
(the internal bandgap 2.5 V reference) and 0 V to AVDD. It can
operate in 12-bit or 8-bit mode. The DAC has a control regis-
ter, DACCON, and two data registers, DACH/L. The DAC
output can be programmed to appear at Pin 3 or Pin 12. It
should be noted that in 12-bit mode, the DAC voltage output
will be updated as soon as the DACL data SFR has been writ-
ten; therefore, the DAC data registers should be updated as
DACH first followed by DACL.
5
DACCON
DAC Control Register
SFR Address
FDH
Power-On Default Value
00H
Bit Addressable
No
-
--
-
--
-
-N
I
P
C
A
D8
C
A
DN
R
C
A
D
R
L
C
A
D
N
E
C
A
D
Table XIV. DACCON SFR Bit Designations
Bit
Name
Description
7
---
Reserved for Future Use.
6
---
Reserved for Future Use.
5
---
Reserved for Future Use.
4
DACPIN
DAC Output Pin Select.
Set by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).
3
DAC8
DAC 8-bit Mode Bit.
Set by user to enable 8-bit DAC operation. In this mode the 8-bits in DACL SFR are routed to
the 8 MSBs of the DAC and the 4 LSBs of the DAC are set to zero.
Cleared by user to operate the DAC in its normal 12-bit mode of operation.
2
DACRN
DAC Output Range Bit.
Set by user to configure DAC range of 0 – AVDD.
Cleared by user to configure DAC range of 0 – 2.5 V.
1
DACCLR
DAC Clear Bit.
Set to “1” by user to enable normal DAC operation.
Cleared to “0” by user to reset DAC data registers DACl/H to zero.
0
DACEN
DAC Enable Bit.
Set to “1” by user to enable normal DAC operation.
Cleared to “0” by user to power-down the DAC.
DACH/L
DAC Data Registers
Function
DAC Data Registers, written by user to update the DAC output.
SFR Address
DACL (DAC Data Low Byte)
–>FBH
DACH (DAC Data High Byte)
–>FCH
Power-On Default Value
00H
–>Both Registers
Bit Addressable
No
–>Both Registers
The 12-bit DAC data should be written into DACH/L right-justified such that DACL contains the lower eight bits, and the lower
nibble of DACH contains the upper four bits.
REV. A
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