參數(shù)資料
型號： ADUC7061BCPZ32
廠商： Analog Devices Inc
文件頁數(shù)： 70/108頁
文件大?。?/td> 0K
描述： IC MCU 16/32BIT 32KB 32LFCSP
產(chǎn)品培訓模塊： Weigh Scale Introduction
產(chǎn)品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設計資源： USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075)
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 8
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
包裝： 管件
產(chǎn)品目錄頁面： 739 (CN2011-ZH PDF)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 64 of 108
FIQSTAN
If IRQCONN[1] is asserted and FIQVEC is read, then one of
these bits asserts. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0, Bit 0 asserts; Priority 1, Bit 1
asserts; and so forth.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is possible to clear only one bit as a time. For
example, if this register is set to 0x09, writing 0xFF changes the
register to 0x08, and writing 0xFF a second time changes the
register to 0x00.
FIQSTAN Register
Name:
FIQSTAN
Address:
0xFFFF013C
Default value: 0x00000000
Access:
Read and write
Table 75. FIQSTAN MMR Bit Designations
Bit
Name
Description
31:8
Reserved
These bits are reserved and should not be
written to.
7:0
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
External Interrupts (IRQ0 to IRQ3)
The ADuC706x provides up to four external interrupt sources.
These external interrupts can be individually configured as level
triggered or rising/falling edge triggered.
To enable the external interrupt source, the appropriate bit must
first be set in the FIQEN or IRQEN register. To select the
required edge or level to trigger on, the IRQCONE register
must be appropriately configured.
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in the IRQCLRE register.
IRQCONE Register
Name:
IRQCONE
Address:
0xFFFF0034
Default value:
0x00000000
Access:
Read and write
Table 76. IRQCONE MMR Bit Designations
Bit
Name
Description
31:8
Reserved
These bits are reserved and should not be written to.
7:6
IRQ3SRC[1:0]
[11] = External IRQ3 triggers on falling edge.
[10] = External IRQ3 triggers on rising edge.
[01] = External IRQ3 triggers on low level.
[00] = External IRQ3 triggers on high level.
5:4
IRQ2SRC[1:0]
[11] = External IRQ2 triggers on falling edge.
[10] = External IRQ2 triggers on rising edge.
[01] = External IRQ2 triggers on low level.
[00] = External IRQ2 triggers on high level.
3:2
IRQ1SRC[1:0]
[11] = External IRQ1 triggers on falling edge.
[10] = External IRQ1 triggers on rising edge.
[01] = External IRQ1 triggers on low level.
[00] = External IRQ1 triggers on high level.
1:0
IRQ0SRC[1:0]
[11] = External IRQ0 triggers on falling edge.
[10] = External IRQ0 triggers on rising edge.
[01] = External IRQ0 triggers on low level.
[00] = External IRQ0 triggers on high level.
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