參數(shù)資料
型號： ADUC7060BCPZ32
廠商： Analog Devices Inc
文件頁數(shù)： 27/108頁
文件大?。?/td> 0K
描述： IC MCU 24BIT 32KB FLASH 48LFCSP
設(shè)計資源： 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Low power, Long Range, ISM Wireless Measuring Node (CN0164)
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 14
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 托盤
Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 25 of 108
FEEDAT Register
FEEDAT is a 16-bit data register. This register holds the data
value for flash read and write commands.
Name:
FEEDAT
Address:
0xFFFF0E0C
Default value:
0xXXXX
Access:
Read and write
FEEADR Register
FEEADR is a 16-bit address register used for accessing
individual pages of the 32 kB flash block. The valid address
range for a user is: 0x0000 to 0x77FF. This represents the 30 kB
flash user memory space. A read or write access outside this
boundary causes a data abort exception to occur.
Name:
FEEADR
Address:
0xFFFF0E10
Default value:
0x0000
Access:
Read and write
FEESIGN Register
The FEESIGN register is a 24-bit MMR. This register is updated
with the 24-bit signature value after the signature command is
executed. This value is the result of the linear feedback shift
register (LFSR) operation initiated by the signature command.
Name:
FEESIGN
Address:
0xFFFF0E18
Default value:
0xFFFFFF
Access:
Read
FEEPRO Register
The FEEPRO MMR provides protection following a subsequent
reset of the MMR. It requires a software key (see Table 16).
Name:
FEEPRO
Address:
0xFFFF0E1C
Default value:
0x00000000
Access:
Read and write
FEEHIDE Register
The FEEHIDE MMR provides immediate protection. It does
not require any software key. Note that the protection settings
in FEEHIDE are cleared by a reset (see Table 16).
Name:
FEEHIDE
Address:
0xFFFF0E20
Default value:
0xFFFFFFFF
Access:
Read and write
Table 16. FEEPRO and FEEHIDE MMR Bit Designations
Bit
Description
31
Read protection.
Cleared by user to protect all code. No JTAG read
accesses for protected pages if this bit is cleared.
Set by the user to allow reading the code via JTAG.
30
Protection for Page 59 (0x00087600 to 0x000877FF).
Set by the user to allow writing to Page 59. Cleared to
protect Page 59.
29
Protection for Page 58 (0x00087400 to 0x000875FF).
Set by the user to allow writing to Page 58. Cleared to
protect Page 58.
28:0
Write protection for Page 57 to Page 0. Each bit
represents two pages. Each page is 512 bytes in size.
Bit 0 is protection for Page 0 and Page 1 (0x00080000
to 0x000803FF). Set by the user to allow writing Page 0
and Page 1. Cleared to protect Page 0 and Page 1.
Bit 1 is protection for Page 2 and Page 3 (0x00080400
to 0x000807FF. Set by the user to allow writing Page 2
and Page 3. Cleared to protect Page 2 and Page 3.
…
Bit 27 is protection for page 54 and page 55 (0x86C00
to 0x86FFF). Set by the user to allow writing to Page
54 and Page 55. Cleared to protect Page 54 and Page
55.
Bit 28 is protection for page 56 and page 57 (0x87000
to 0x873FF). Set by the user to allow writing to Page
56 and Page 57. Cleared to protect Page 56 and Page
57.
Temporary Protection
Temporary protection can be set and removed by writing
directly into the FEEHID MMR. This register is volatile and,
therefore, protection is only in place for as long as the part
remains powered on. The protection setting is not reloaded
after a power cycle.
Keyed Permanent Protection
Keyed permanent protection can be set via FEEPRO to lock the
protection configuration. The software key used at the start of
the required FEEPRO write sequence is saved one time only
and must be used for any subsequent access of the FEEHID or
FEEPRO MMRs. A mass erase sets the software protection key
back to 0xFFFF but also erases the entire user code space.
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