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| 型號： | ADUC7026BSTZ62 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 62K W/ANLG 80LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12 x12b; D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 托盤 |
| 配用： | EVAL-ADUC7026QSPZ-ND - KIT DEV ADUC7026/7027 QUICK PLUS EVAL-ADUC7026QSZ-ND - KIT DEV FOR ADUC7026/7027 |
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ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 54 of 104
EXECUTION TIME FROM SRAM AND FLASH/EE
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle; the
access time of the SRAM is 2 ns, and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE): one
cycle to execute the instruction, and two cycles to get the 32-bit
data from Flash/EE. A control flow instruction (a branch
instruction, for example) takes one cycle to fetch but also takes
two cycles to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 22 ns, execution from Flash/EE cannot be done in
one cycle (as can be done from SRAM when the CD Bit = 0).
Also, some dead times are needed before accessing data for any
value of the CD bit.
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter, and
then four cycles are needed to fill the pipeline. A data-processing
instruction involving only the core register does not require any
extra clock cycles. However, if it involves data in Flash/EE, an
extra clock cycle is needed to decode the address of the data,
and two cycles are needed to get the 32-bit data from Flash/EE.
An extra cycle must also be added before fetching another
instruction. Data transfer instructions are more complex and
are summarized in Table 43.
Table 43. Execution Cycles in ARM/Thumb Mode
Instructions
Fetch
Cycles
Dead
Time
Data Access
Dead
Time
2/1
1
2
1
LDH
2/1
1
LDM/PUSH
2/1
2 × N2
STR1
2/1
1
2 × 20 ns
1
STRH
2/1
1
20 ns
1
STRM/POP
2/1
2 × N × 20 ns1
1
The SWAP instruction combines an LD and STR instruction with only one
fetch, giving a total of eight cycles + 40 ns.
2
N is the amount of data to load or store in the multiple load/store instruction
(1 < N ≤ 16).
RESET AND REMAP
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020,
as shown in Figure 62.
04955-
022
KERNEL
INTERRUPT
SERVICE ROUTINES
INTERRUPT
SERVICE ROUTINES
ARM EXCEPTION
VECTOR ADDRESSES
0x00000020
0x00011FFF
0x0008FFFF
0xFFFFFFFF
FLASH/EE
SRAM
MIRROR SPACE
0x00000000
0x00010000
0x00080000
Figure 62. Remap for Exception Execution
By default, and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, which facilitates execution of exception routines from
SRAM instead of from Flash/EE. This means exceptions are
executed twice as fast, being executed in 32-bit ARM mode with
32-bit wide SRAM instead of 16-bit wide Flash/EE memory.
Remap Operation
When a reset occurs on the ADuC7019/20/21/22/24/25/26/27/
28/29, execution automatically starts in the factory-programmed,
internal configuration code. This kernel is hidden and cannot
be accessed by user code. If the part is in normal mode (the BM
pin is high), it executes the power-on configuration routine of
the kernel and then jumps to the reset vector address,
0x00000000, to execute the user’s reset exception routine.
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset interrupt routine must always be written
in Flash/EE.
The remap is done from Flash/EE by setting Bit 0 of the REMAP
register. Caution must be taken to execute this command from
Flash/EE, above Address 0x00080020, and not from the bottom
of the array because this is replaced by the SRAM.
This operation is reversible. The Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the REMAP MMR.
Caution must again be taken to execute the remap function
from outside the mirrored area. Any type of reset remaps the
Flash/EE memory at the bottom of the array.
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