參數(shù)資料
型號(hào)： ADUC7020BCPZ62I
廠商： Analog Devices Inc
文件頁數(shù)： 69/104頁
文件大?。?/td> 0K
描述： IC MCU FLSH 62K ANLG I/O 40LFCSP
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PLA，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 14
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x12b; D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
包裝： 托盤
配用： EVAL-ADUC7020QSZ-ND - KIT DEV ADUC7020 QUICK START
EVAL-ADUC7020MKZ-ND - KIT MINI DEV FOR ADUC7020
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 67 of 104
Table 70. PWMCFG Register
Name
Address
Default Value
Access
PWMCFG
0xFFFFFC10
0x0000
R/W
PWMCFG is a gate chopping register.
Table 71. PWMCFG MMR Bit Descriptions
Bit
Name
Description
15:10
Reserved.
9
CHOPLO
Low-side gate chopping enable bit.
8
CHOPHI
High-side gate chopping enable bit.
7:0
GDCLK
PWM gate chopping period (unsigned).
Table 72. PWMEN Register
Name
Address
Default Value
Access
PWMEN
0xFFFFFC20
0x0000
R/W
PWMEN allows enabling of channel outputs and crossover. See
its bit definitions in Table 73.
Table 73. PWMEN MMR Bit Descriptions
Bit
Name
Description
8
0H0L_XOVR
Channel 0 output crossover enable bit.
Set to 1 by user to enable Channel 0 output
crossover. Cleared to 0 by user to disable
Channel 0 output crossover.
7
1H1L_XOVR
Channel 1 output crossover enable bit.
Set to 1 by user to enable Channel 1 output
crossover. Cleared to 0 by user to disable
Channel 1 output crossover.
6
2H2L_XOVR
Channel 2 output crossover enable bit.
Set to 1 by user to enable Channel 2 output
crossover. Cleared to 0 by user to disable
Channel 2 output crossover.
5
0L_EN
0L output enable bit. Set to 1 by user to
disable the 0L output of the PWM. Cleared to 0
by user to enable the 0L output of the PWM.
4
0H_EN
0H output enable bit. Set to 1 by user to
disable the 0H output of the PWM. Cleared to
0 by user to enable the 0H output of the PWM.
3
1L_EN
1L output enable bit. Set to 1 by user to
disable the 1L output of the PWM. Cleared to 0
by user to enable the 1L output of the PWM.
2
1H_EN
1H Output Enable Bit. Set to 1 by user to
disable the 1H output of the PWM. Cleared to
0 by user to enable the 1H output of the PWM.
1
2L_EN
2L output enable bit. Set to 1 by user to
disable the 2L output of the PWM. Cleared to 0
by user to enable the 2L output of the PWM.
0
2H_EN
2H output enable bit. Set to 1 by user to
disable the 2H output of the PWM. Cleared to
0 by user to enable the 2H output of the PWM.
Table 74. PWMDAT0 Register
Name
Address
Default Value
Access
PWMDAT0
0xFFFFFC08
0x0000
R/W
PWMDAT0 is an unsigned 16-bit register for switching period.
Table 75. PWMDAT1 Register
Name
Address
Default Value
Access
PWMDAT1
0xFFFFFC0C
0x0000
R/W
PWMDAT1 is an unsigned 10-bit register for dead time.
Table 76. PWMCHx Registers
Name
Address
Default Value
Access
PWMCH0
0xFFFFFC14
0x0000
R/W
PWMCH1
0xFFFFFC18
0x0000
R/W
PWMCH2
0xFFFFFC1C
0x0000
R/W
PWMCH0, PWMCH1, and PWMCH2 are channel duty cycles
for the three phases.
Table 77. PWMDAT2 Register
Name
Address
Default Value
Access
PWMDAT2
0xFFFFFC24
0x0000
R/W
PWMDAT2 is an unsigned 10-bit register for PWM sync
pulse width.
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7019/20/21/22/24/25/26/27/28/29 provide 40 general-
purpose, bidirectional I/O (GPIO) pins. All I/O pins are 5 V
tolerant, meaning the GPIOs support an input voltage of 5 V.
In general, many of the GPIO pins have multiple functions (see
Table 78 for the pin function definitions). By default, the GPIO
pins are configured in GPIO mode.
All GPIO pins have an internal pull-up resistor (of about
100 k), and their drive capability is 1.6 mA. Note that a
maximum of 20 GPIOs can drive 1.6 mA at the same time.
Using the GPxPAR registers, it is possible to enable/disable
the pull-up resistors for the following ports: P0.0, P0.4, P0.5,
P0.6, P0.7, and the eight GPIOs of P1.
The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x).
Each port is controlled by four or five MMRs.
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to ensure
that the level on P0.6 does not drop when the kernel switches
mode. Otherwise, P0.6 goes low for the reset period. For
example, if MRST is required for power-down, it can be
reconfigured in GP0CON MMR.
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a mode
other than GPIO. The PLA input is always active.
When the ADuC7019/20/21/22/24/25/26/27/28/29 part enters a
power-saving mode, the GPIO pins retain their state.
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ADUC7020SRTZ 制造商:Analog Devices 功能描述:
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