參數(shù)資料
    型號(hào): ADT7519ARQ
    廠商: ANALOG DEVICES INC
    元件分類: 溫度/濕度傳感器
    英文描述: SPI/I2C Compatible, Temperature Sensor, Four Channel ADC and Quad Voltage Output DAC
    中文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 1Cel, RECTANGULAR, SURFACE MOUNT
    封裝: MO-137AB, QSOP-16
    文件頁(yè)數(shù): 37/44頁(yè)
    文件大小: 1350K
    代理商: ADT7519ARQ
    ADT7516/ADT7517/ADT7519
    AIN3 V
    LOW
    Limit Register (Read/Write) [Add. = 2Eh]
    This limit register is an 8-bit read/write register that stores the
    AIN3 input lower limit, which will cause an interrupt and
    activate the INT/INT output (if enabled). For this to happen,
    the measured AIN3 value has to be less than or equal to the
    value in this register. Because it is an 8-bit register, the reso-
    lution is four times less than the resolution of the 10-bit ADC.
    The default value is 0 V.
    Table 64. AIN3 V
    LOW
    Limit
    D7
    D6
    D5
    D4
    D7
    D6
    D5
    D4
    0*
    0*
    0*
    0*
    Rev. A | Page 37 of 44
    D3
    D3
    0*
    D2
    D2
    0*
    D1
    D1
    0*
    D0
    D0
    0*
    *Default settings at power-up.
    AIN4 V
    HIGH
    Limit Register (Read/Write) [Add. = 2Fh]
    This limit register is an 8-bit read/write register that stores the
    AIN4 input upper limit, which will cause an interrupt and acti-
    vate the INT/INT output (if enabled). For this to happen, the
    measured AIN4 value has to be greater than the value in this
    register. Because it is an 8-bit register, the resolution is four
    times less than the resolution of the 10-bit ADC. The default
    value is full-scale voltage.
    Table 65. AIN4 V
    HIGH
    Limit
    D7
    D6
    D5
    D4
    D7
    D6
    D5
    D4
    1*
    1*
    1*
    1*
    D3
    D3
    1*
    D2
    D2
    1*
    D1
    D1
    1*
    D0
    D0
    1*
    *Default settings at power-up.
    AIN4 V
    LOW
    Limit Register (Read/Write) [Add. = 30h]
    This limit register is an 8-bit read/write register that stores the
    AIN4 input lower limit, which will cause an interrupt and
    activate the INT/INT output (if enabled). For this to happen,
    the measured AIN4 value has to be less than or equal to the
    value in this register. Because it is an 8-bit register, the reso-
    lution is four times less than the resolution of the 10-bit ADC.
    The default value is 0 V.
    Table 66. AIN4 V
    LOW
    Limit
    D7
    D6
    D5
    D4
    D7
    D6
    D5
    D4
    0*
    0*
    0*
    0*
    D3
    D3
    0*
    D2
    D2
    0*
    D1
    D1
    0*
    D0
    D0
    0*
    *Default settings at power-up.
    Device ID Register (Read-Only) [Add. = 4Dh]
    This 8-bit read-only register indicates which part the device is
    in the model range. ADT7516 = 03h, ADT7517 = 07h, and
    ADT7519 = 0Bh.
    Manufacturer’s ID Register (Read-Only) [Add. = 4Eh]
    This register contains the manufacturer’s identification number.
    ADI’s ID number is 41h.
    Silicon Revision Register (Read-Only) [Add. = 4Fh]
    This register is divided into the four LSBs representing the
    stepping and the four MSBs representing the version. The
    stepping contains the manufacturer’s code for minor revisions
    or steppings to the silicon. The version is the ADT7516/
    ADT7517/ADT7519 version number.
    SPI Lock Status Register (Read-Only) [Add. = 7Fh]
    Bit D0 (LSB) of this read-only register indicates whether or not
    the SPI interface is locked. Writing to this register will cause the
    device to malfunction. The default value is 00h.
    0 = I
    2
    C interface.
    1 = SPI interface selected and locked.
    SERIAL INTERFACE
    There are two serial interfaces that can be used on this part: I
    2
    C
    and SPI. The device will power up with the serial interface in
    I
    2
    C mode, but it is not locked into this mode. To stay in I
    2
    C
    mode, it is recommended that the user tie the CS line to either
    V
    CC
    or GND. It is not possible to lock the I
    2
    C mode, but it is
    possible to select and lock the SPI mode.
    To select and lock the interface into the SPI mode, a number of
    pulses must be sent down the CS line (Pin 4). The following
    section describes how this is done.
    Once the SPI communication protocol has been locked in, it
    cannot be unlocked while the device is still powered up. Bit D0
    of the SPI lock status register (Address 7Fh) is set to 1 when a
    successful SPI interface lock has been accomplished. To reset
    the serial interface, the user must power down the part and
    power it up again. A software reset does not reset the serial
    interface.
    Serial Interface Selection
    The CS line controls the selection between I
    2
    C and SPI.
    Figure 59 shows the selection process necessary to lock the SPI
    interface mode.
    To communicate to the ADT7516/ADT7517/ADT7519 using
    the SPI protocol, send three pulses down the CS line as shown
    in Figure 59. On the third rising edge (marked as C in
    Figure 59), the part selects and locks the SPI interface. The user
    is now limited to communicating to the device using the SPI
    protocol.
    As per most SPI standards, the CS line must be low during
    every SPI communication to the ADT7516/ADT7517/
    ADT7519 and high all other times. Typical examples of how to
    connect the dual interface as I
    2
    C or SPI is shown in Figure 57
    and Figure 58. The following sections describe in detail how to
    use the I
    2
    C and SPI protocols associated with the ADT7516/
    ADT7517/ADT7519.
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