DS2–08 Static Pins—Must Be Constant —
參數(shù)資料
型號(hào)： ADSP-TS201SABP-060
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/48頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR 600MHZ 576BGA
標(biāo)準(zhǔn)包裝： 1
系列： TigerSHARC®
類型： 定點(diǎn)/浮點(diǎn)
接口： 主機(jī)接口，連接端口，多處理器
時(shí)鐘速率： 600MHz
非易失內(nèi)存： 外部
芯片上RAM： 3MB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 576-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 576-BGA-ED（25x25）
包裝： 托盤
配用： ADZS-TS201S-EZLITE-ND - KIT LITE EVAL FOR ADSP-TS201S
ADSP-TS201S
Rev. C
|
Page 29 of 48
|
December 2006
DS2–08
Static Pins—Must Be Constant
—
SCLKRAT2–08
Static Pins—Must Be Constant
—
ENEDREG
Static Pins—Must Be Connected to VSS
——
—
STRAP SYS
9, 10
Strap Pins
1.5
0.5
——
SCLK
JTAG SYS
11, 12
JTAG System Pins
+2.5
+10.0
+12.0
–1.0
—
TCK
1 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave access boundary crossings to avoid any potential bus contention. The
apparent driver overlap, due to output disables being larger than output enables, is not actual.
2 For input specifications on FLAG3–0 pins, see Table 21.
3 These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.
4 For additional requirement details, see Reset and Booting on Page 9.
5 RST_IN clock reference is the falling edge of SCLK.
6 TDO output clock reference is the falling edge of TCK.
7 Reference clock depends on function.
8 These pins may change only during reset; recommend connecting it to VDD_IO/VSS.
9 STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO.
10Specifications applicable during reset only.
11JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10,
IOEN, BUSLOCK, TMR0E, DATA63–0, ADDR31–0, RD, WRL, WRH, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0,
L1DATOP3–0, L1DATON3–0, L2DATOP3–0, L2DATON3–0, L3DATOP3–0, L3DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP,
L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L2DATIP3–0,
L2DATIN3–0, L3DATIP3–0, L3DATIN3–0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO,
L2ACKO, L3ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2–0, CTRL_IMPD1–0,
SCLKRAT2–0, DS2–0, ENEDREG.
12JTAG system output timing clock reference is the falling edge of TCK.
Figure 15. General AC Parameters Timing
Table 29. AC Signal Specifications (Continued)
(All values in this table are in nanoseconds.)
Name
Description
In
put
S
e
tu
p
(M
in
)
In
put
Hold
(M
in
)
Ou
tp
u
tV
a
li
d
(M
a
x
)
Ou
tp
u
tH
o
ld
(M
in
)
Ou
tp
u
tEn
ab
le
(M
in
)1
Ou
tpu
tDi
sab
le
(M
a
x
)1
Re
fe
re
nce
Cl
ock
REFERENCE
CLOCK
INPUT
SIGNAL
OUTPUT
SIGNAL
THREE-
STATE
OUTPUT
VALID
OUTPUT
HOLD
OUTPUT
ENABLE
OUTPUT
DISABLE
INPUT
HOLD
INPUT
SETUP
1.25V
tSCLK OR tTCK
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ADSP-TS201SABPZ050 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
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