參數(shù)資料
型號(hào): ADSP-BF592KCPZ-2
廠商: Analog Devices Inc
文件頁(yè)數(shù): 20/44頁(yè)
文件大?。?/td> 0K
描述: IC DSP CTRLR 200MHZ 64LFCSP
視頻文件: Blackfin? BF592 Introduction
特色產(chǎn)品: Blackfin Embedded Processor
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點(diǎn)
接口: I²C,I²S,IrDA,PPI,SPI,SPORT,UART
時(shí)鐘速率: 200MHz
非易失內(nèi)存: ROM(64 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.29V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤(pán)
Rev. B
|
Page 27 of 44
|
July 2013
Figure 14. Serial Ports
Figure 15. Serial Port Start Up with External Clock and Frame Sync
tSDRI
RSCLKx
DRx
DRIVE EDGE
tHDRI
tSFSI
tHFSI
tDFSI
tHOFSI
tSCLKIW
DATA RECEIVE—INTERNAL CLOCK
tSDRE
DATA RECEIVE—EXTERNAL CLOCK
RSCLKx
DRx
tHDRE
tSFSE
tHFSE
tDFSE
tSCLKEW
tHOFSE
tDDTI
tHDTI
TSCLKx
TFSx
(INPUT)
DTx
tSFSI
tHFSI
tSCLKIW
tDFSI
tHOFSI
DATA TRANSMIT—INTERNAL CLOCK
tDDTE
tHDTE
TSCLKx
DTx
tSFSE
tDFSE
t SCLKEW
tHOFSE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
tSCLKE
tHFSE
TFSx
(OUTPUT)
TFSx
(INPUT)
TFSx
(OUTPUT)
RFSx
(INPUT)
RFSx
(OUTPUT)
RFSx
(INPUT)
RFSx
(OUTPUT)
TSCLKx
(INPUT)
TFSx
(INPUT)
RFSx
(INPUT)
RSCLKx
(INPUT)
tSUDTE
tSUDRE
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED
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