參數(shù)資料
型號(hào)： ADSP-BF548MBBCZ-5M
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/100頁(yè)
文件大小： 0K
描述： IC DSP 533MHZ W/DDR 400CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： CAN，SPI，SSP，TWI，UART，USB
時(shí)鐘速率： 533MHz
非易失內(nèi)存： 外部
芯片上RAM： 260kB
電壓 - 輸入/輸出： 2.50V，3.30V
電壓 - 核心： 1.25V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 400-CSPBGA（17x17）
包裝： 托盤
配用： ADSP-3PARCBF548M01-ND - MODULE BOARD BF548
ADSP-3PARCBF548E02-ND - KIT DEV STARTER BF548
Rev. C
|
Page 34 of 100
|
February 2010
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
SPECIFICATIONS
Component specifications are subject to change without notice.
OPERATING CONDITIONS
Parameter
Conditions
Min
Nominal
Max
Unit
VDDINT
1, 2
Internal Supply Voltage
Nonautomotive grade models
0.9
1.43
V
Internal Supply Voltage
Automotive grade models
1.0
1.38
V
Internal Supply Voltage
Mobile DDR SDRAM models
1.14
1.31
V
VDDEXT
3
External Supply Voltage
Nonautomotive 3.3 V I/O
2.7
3.3
3.6
V
External Supply Voltage
Nonautomotive 2.5 V I/O
2.25
2.5
2.75
V
External Supply Voltage
Automotive grade models
2.7
3.3
3.6
V
VDDUSB
USB External Supply Voltage
3.0
3.3
3.6
V
VDDMP
MXVR PLL Supply Voltage
Nonautomotive grade models
0.9
1.43
V
MXVR PLL Supply Voltage
Automotive grade models
1.0
1.38
V
VDDRTC
Real Time Clock Supply Voltage
Nonautomotive grade models
2.25
3.6
V
Real Time Clock Supply Voltage
Automotive grade models
2.7
3.3
3.6
V
VDDDDR
DDR Memory Supply Voltage
DDR SDRAM models
2.5
2.6
2.7
V
DDR Memory Supply Voltage
Mobile DDR SDRAM models
1.8
1.875
1.95
V
VDDVR
4
Internal Voltage Regulator
Supply Voltage
2.7
3.3
3.6
V
VIH
High Level Input Voltage5, 6
VDDEXT =maximum
2.0
3.6
V
VIHDDR
High Level Input Voltage7
DDR SDRAM models
VDDR_VREF + 0.15
VDDDDR + 0.3
V
High Level Input Voltage7
Mobile DDR SDRAM models
VDDR_VREF + 0.125
VDDDDR + 0.3
V
VIH5V
High Level Input Voltage
8
VDDEXT =maximum
2.0
5.5
V
VIHTWI
High Level Input Voltage
9, 13
VDDEXT = maximum
0.7 x VDDEXT
5.5
V
VIHUSB
High Level Input Voltage
10
5.25
V
VIL
Low Level Input Voltage5, 11
VDDEXT = minimum
–0.3
0.6
V
VIL5V
Low Level Input Voltage12
3.3 V I/O, VDDEXT = minimum
–0.3
0.8
V
Low Level Input Voltage12
2.5 V I/O, VDDEXT = minimum
–0.3
0.6
V
VILDDR
Low Level Input Voltage
DDR SDRAM models
–0.3
VDDR_VREF – 0.15
V
Low Level Input Voltage
Mobile DDR SDRAM models
–0.3
VDDR_VREF – 0.125 V
VILTWI
Low Level Input Voltage
9, 13
–0.3
0.3 x VDDEXT
V
VDDR_VREF
DDR_VREF Pin Input Voltage
0.49 x VDDDDR
0.50 x
VDDDDR
0.51 x VDDDDR
V
TJ
14
Junction Temperature
(400/533 MHz)
400-Ball Chip Scale Package Ball
Grid Array (CSP_BGA) @TAMBIENT =
–40C to +85C
–40
+105
C
Junction Temperature (600 MHz) 400-Ball Chip Scale Package Ball
Grid Array (CSP_BGA) @TAMBIENT =
0
C to +70C
0+90
C
1 See Table 13 on Page 35 for frequency/voltage specifications.
2 VDDINT maximum is 1.10 V during one-time-programmable (OTP) memory programming operations.
3 VDDEXT minimum is 3.0 V and maximum is 3.6 V during OTP memory programming operations.
4 Use of the internal voltage regulator is not supported on 600 MHz speed grade models or on automotive grade models. An external voltage regulator must be used.
5 Bidirectional pins (D15–0, PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0) and input pins (ATAPI_PDIAG, USB_ID, TCK, TDI,
TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF54x Blackfin processors are 3.3 V-tolerant (always accept up to 3.6 V maximum VIH). Voltage
compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. The regulator can generate VDDINT at levels of 0.90 V to 1.30 V with -5% to +5% tolerance.
6 Parameter value applies to all input and bidirectional pins except PB1-0, PE15-14, PG15–11, PH7-6, DQ0-15, and DQS0-1.
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