Figure 59. Typical Output Delay or Hold for Driver E at V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ADSP-BF536BBC-3A
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 51/68闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC DSP CTLR 16BIT 182CSPBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� Blackfin®
椤炲瀷锛� 瀹氶粸
鎺ュ彛锛� CAN锛孲PI锛孲SP锛孴WI锛孶ART
鏅傞悩閫熺巼锛� 300MHz
闈炴槗澶卞収(n猫i)瀛橈細 澶栭儴
鑺墖涓奟AM锛� 100kB
闆诲 - 杓稿叆/杓稿嚭锛� 2.50V锛�3.30V
闆诲 - 鏍稿績锛� 1.20V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 182-LFBGA锛孋SPBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 182-CSPBGA锛�12x12锛�
鍖呰锛� 鎵樼洡
Rev. J
|
Page 55 of 68
|
February 2014
Figure 59. Typical Output Delay or Hold for Driver E at VDDEXT Min
Figure 60. Typical Output Delay or Hold for Driver E at VDDEXT Max
LOAD CAPACITANCE (pF)
RISE TIME
RISE
AND
F
ALL
TIME
ns
(10%
to
90%)
36
32
28
24
20
16
12
8
4
0
50
100
150
200
250
FALL TIME
LOAD CAPACITANCE (pF)
RISE TIME
RISE
AND
F
ALL
TIME
ns
(10%
to
90%)
36
32
28
24
20
16
12
8
4
0
50
100
150
200
250
FALL TIME
Figure 61. Typical Output Delay or Hold for Driver F at VDDEXT Min
Figure 62. Typical Output Delay or Hold for Driver F at VDDEXT Max
LOAD CAPACITANCE (pF)
RISE TIME
RISE
AND
F
ALL
TIME
ns
(10%
to
90%)
36
32
28
24
20
16
12
8
4
0
50
100
150
200
250
FALL TIME
LOAD CAPACITANCE (pF)
RISE TIME
RISE
AND
F
ALL
TIME
ns
(10%
to
90%)
36
32
28
24
20
16
12
8
4
0
50
100
150
200
250
FALL TIME
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
HWS150-12/ME PWRSUP IND MEDICAL 12V 156W 13A
VE-B6F-EU-B1 CONVERTER MOD DC/DC 72V 200W
HWS150-48/ME PWRSUP IND MED 48V 158.4W 3.3A
RW2-1215D/H3 CONV DC/DC 2W 9-18VIN +/-15VOUT
RMA40DRMD-S288 CONN EDGECARD 80POS .125 EXTEND
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鍙冩暩(sh霉)鎻忚堪
ADSP-BF536BBC-4A 鍔熻兘鎻忚堪:IC DSP CTLR 16BIT 182CSPBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - DSP锛堟暩(sh霉)瀛楀紡淇¤櫉铏曠悊鍣級 绯诲垪:Blackfin® 妯�(bi膩o)婧�(zh菙n)鍖呰:2 绯诲垪:StarCore 椤炲瀷:SC140 鍏�(n猫i)鏍� 鎺ュ彛:DSI锛屼互澶恫(w菐ng)锛孯S-232 鏅傞悩閫熺巼:400MHz 闈炴槗澶卞収(n猫i)瀛�:澶栭儴 鑺墖涓奟AM:1.436MB 闆诲 - 杓稿叆/杓稿嚭:3.30V 闆诲 - 鏍稿績:1.20V 宸ヤ綔婧害:-40°C ~ 105°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:431-BFBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:431-FCPBGA锛�20x20锛� 鍖呰:鎵樼洡
ADSP-BF536BBCZ-3A 鍔熻兘鎻忚堪:IC DSP CTLR 16BIT 182CSPBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - DSP锛堟暩(sh霉)瀛楀紡淇¤櫉铏曠悊鍣級 绯诲垪:Blackfin® 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:TMS320DM64x, DaVinci™ 椤炲瀷:瀹氶粸 鎺ュ彛:I²C锛孧cASP锛孧cBSP 鏅傞悩閫熺巼:400MHz 闈炴槗澶卞収(n猫i)瀛�:澶栭儴 鑺墖涓奟AM:160kB 闆诲 - 杓稿叆/杓稿嚭:3.30V 闆诲 - 鏍稿績:1.20V 宸ヤ綔婧害:0°C ~ 90°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:548-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:548-FCBGA锛�27x27锛� 鍖呰:鎵樼洡 閰嶇敤:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP-BF536BBCZ-3AX 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:182-MBGA PB-FREE - Trays
ADSP-BF536BBCZ-3B 鍔熻兘鎻忚堪:IC DSP CTLR 16BIT 208CSPBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - DSP锛堟暩(sh霉)瀛楀紡淇¤櫉铏曠悊鍣級 绯诲垪:Blackfin® 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:TMS320DM64x, DaVinci™ 椤炲瀷:瀹氶粸 鎺ュ彛:I²C锛孧cASP锛孧cBSP 鏅傞悩閫熺巼:400MHz 闈炴槗澶卞収(n猫i)瀛�:澶栭儴 鑺墖涓奟AM:160kB 闆诲 - 杓稿叆/杓稿嚭:3.30V 闆诲 - 鏍稿績:1.20V 宸ヤ綔婧害:0°C ~ 90°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:548-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:548-FCBGA锛�27x27锛� 鍖呰:鎵樼洡 閰嶇敤:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP-BF536BBCZ3BRL 鍔熻兘鎻忚堪:IC DSP CTLR 16BIT 208BGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - DSP锛堟暩(sh霉)瀛楀紡淇¤櫉铏曠悊鍣級 绯诲垪:Blackfin® 妯�(bi膩o)婧�(zh菙n)鍖呰:2 绯诲垪:StarCore 椤炲瀷:SC140 鍏�(n猫i)鏍� 鎺ュ彛:DSI锛屼互澶恫(w菐ng)锛孯S-232 鏅傞悩閫熺巼:400MHz 闈炴槗澶卞収(n猫i)瀛�:澶栭儴 鑺墖涓奟AM:1.436MB 闆诲 - 杓稿叆/杓稿嚭:3.30V 闆诲 - 鏍稿績:1.20V 宸ヤ綔婧害:-40°C ~ 105°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:431-BFBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:431-FCPBGA锛�20x20锛� 鍖呰:鎵樼洡