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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ADSP-BF512KSWZ-4F4
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 5/68闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DSP 16/32B 400MHZ LP 176LQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� Blackfin®
椤�(l猫i)鍨嬶細 瀹氶粸(di菐n)
鎺ュ彛锛� I²C锛孭PI锛孲PI锛孲PORT锛孶ART/USART
鏅�(sh铆)閻橀€熺巼锛� 400MHz
闈炴槗澶卞収(n猫i)瀛橈細 闁冨瓨锛�4Mb锛�
鑺墖涓奟AM锛� 116kB
闆诲 - 杓稿叆/杓稿嚭锛� 1.8V锛�2.5V锛�3.3V
闆诲 - 鏍稿績锛� 1.30V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
灏佽/澶栨锛� 176-LQFP 瑁搁湶鐒婄洡(p谩n)
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 176-LQFP-EP锛�24x24锛�
鍖呰锛� 鎵樼洡(p谩n)
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. B
|
Page 13 of 68
|
January 2011
TNOM is the duration running at fCCLKNOM
TRED is the duration running at fCCLKRED
VOLTAGE REGULATION INTERFACE
The ADSP-BF51x processors require an external voltage regula-
tor to power the VDDINT domain. To reduce standby power
consumption in the hibernate state, the external voltage regula-
tor can be signaled through EXT_WAKE to remove power from
the processor core. The EXT_WAKE signal is high-true for
power-up and may be connected directly to the low-true shut
down input of many common regulators.
The Power Good (PG) input signal allows the processor to start
only after the internal voltage has reached a chosen level. In this
way, the startup time of the external regulator is detected after
hibernation. For a complete description of the PG functionality,
refer to the ADSP-BF51x Blackfin Processor Hardware Reference.
CLOCK SIGNALS
The ADSP-BF51x processors can be clocked by an external crys-
tal, a sine wave input, or a buffered, shaped clock derived from
an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor CLKIN signal. When an external
clock is used, the XTAL pin/ball must be left unconnected.
Alternatively, because the processor includes an on-chip oscilla-
tor circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 4. A paral-
lel-resonant, fundamental frequency, microprocessor-grade
crystal is connected across the CLKIN and XTAL pins/balls. The
on-chip resistance between the CLKIN pin/ball and the XTAL
pin/ball is in the 500 k惟 range. Further parallel resistors are typ-
ically not recommended. The two capacitors and the series
resistor shown in Figure 4 fine tune phase and amplitude of the
sine frequency.
The capacitor and resistor values shown in Figure 4 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers鈥� load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
A third-overtone crystal can be used for frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 4. A design procedure for third-overtone oper-
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog
Devices website (www.analog.com)鈥攗se site search on
鈥淓E-168.鈥�
The CLKBUF signal is an output signal, which is a buffered ver-
sion of the input clock. This signal is particularly useful in
Ethernet applications to limit the number of required clock
sources in the system. In this type of application, a single
25 MHz or 50 MHz crystal may be applied directly to the pro-
cessor. The 25 MHz or 50 MHz output of CLKBUF can then be
connected to an external Ethernet MII or RMII PHY device.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 5, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 5脳 to 64脳 multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 6脳, but it can be modified
by a software instruction sequence.
On-the-fly frequency changes can be done simply by writing to
the PLL_DIV register. The maximum allowed CCLK and SCLK
rates depend on the applied voltages VDDINT, VDDEXT, and
VDDMEM, and the VCO is always permitted to run up to the fre-
quency specified by the part鈥檚 speed grade. The CLKOUT signal
reflects the SCLK frequency to the off-chip world. It belongs to
the SDRAM interface, but it functions as a reference signal in
other timing specifications as well. While active by default, it
can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL
registers.
Figure 4. External Crystal Connections
Figure 5. Frequency Modification Methods
CLKIN
CLKOUT
XTAL
EN
CLKBUF
TO PLL CIRCUITRY
FOR OVERTONE
OPERATION ONLY:
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0
.
18 pF *
EN
18 pF *
330
*
BLACKFIN
560
PLL
5
u to 64u
梅1 to 15
梅1,2, 4, 8
VCO
CLKIN
鈥淔INE鈥� ADJUSTMENT
REQUIRES PLL SEQUENCING
鈥淐OARSE鈥� ADJUSTMENT
ON-THE-FLY
CCLK
SCLK
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
GBC05DRTH-S93 CONN EDGECARD 10POS DIP .100 SLD
ACM36DRYH-S13 CONN EDGECARD EXTEND 72POS 0.156
ACM30DTBN CONN EDGECARD 60POS R/A .156 SLD
MLP2520S3R3M INDUCTOR MULTILAYER 3.3UH 1008
ADSP-BF524KBCZ-3 IC DSP CTRLR 300MHZ 289CSPBGA
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鍙冩暩(sh霉)鎻忚堪
ADSP-BF514BBCZ-3 鍔熻兘鎻忚堪:IC DSP 16/32B 300MHZ 168CSPBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - DSP锛堟暩(sh霉)瀛楀紡淇¤櫉(h脿o)铏曠悊鍣級 绯诲垪:Blackfin® 妯�(bi膩o)婧�(zh菙n)鍖呰:2 绯诲垪:StarCore 椤�(l猫i)鍨�:SC140 鍏�(n猫i)鏍� 鎺ュ彛:DSI锛屼互澶恫(w菐ng)锛孯S-232 鏅�(sh铆)閻橀€熺巼:400MHz 闈炴槗澶卞収(n猫i)瀛�:澶栭儴 鑺墖涓奟AM:1.436MB 闆诲 - 杓稿叆/杓稿嚭:3.30V 闆诲 - 鏍稿績:1.20V 宸ヤ綔婧害:-40°C ~ 105°C 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 灏佽/澶栨:431-BFBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:431-FCPBGA锛�20x20锛� 鍖呰:鎵樼洡(p谩n)
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