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| 型號： | ADSP-BF506BSWZ-3F |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 400MHZ 1.4V 120LQFP |
| 視頻文件： | Blackfin? BF50x Processor Family |
| 標準包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART |
| 時鐘速率： | 300MHz |
| 非易失內(nèi)存： | 閃存（16MB） |
| 芯片上RAM： | 68kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.29V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP 裸露焊盤 |
| 供應商設(shè)備封裝： | 120-LQFP-EP（14x14） |
| 包裝： | 托盤 |
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Rev. A
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Page 23 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Table 12. ADC—Signal Descriptions (ADSP-BF506F Processor Only)
Signal Name
Type Function
DGND
G
Digital Ground. This is the ground reference point for all digital circuitry on the internal ADC. Both DGND
pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be
at the same potential and must not be more than 0.3 V apart, even on a transient basis.
REF SELECT
I
Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference
is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be
tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be
supplied to the internal ADC through the DCAPA and/or DCAPB pins.
AVDD
P
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the
internal ADC. The AVDD and DVDD voltages should ideally be at the same potential and must not be more
than 0.3 V apart, even on a transient basis. This supply should be decoupled to AGND.
DCAPA, DCAPB (VREF)
I
Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins
to decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip
reference can be taken from these pins and applied externally to the rest of a system. The range of the
external reference is dependent on the analog input range selected.
AGND
G
Analog Ground. Ground reference point for all analog circuitry on the internal ADC. All analog input
signals and any external reference signal should be referred to this AGND voltage. All three of these
AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should
be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
VA1 to VA6
I
Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differ-
ential analog input channel pairs. See Table 53 (Analog Input Type and Channel Selection).
VB1 to VB6
I
Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differ-
ential analog input channel pairs. See Table 53 (Analog Input Type and Channel Selection).
RANGE
I
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the
analog input channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is
tied to a logic high when CS goes low, the analog input range is 2 × VREF. For details, see Table 53 (Analog
SGL/DIFF
I
Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single
ended. A logic low selects differential operation while a logic high selects single-ended operation. For
details, see Table 53 (Analog Input Type and Channel Selection).
A0 to A2
I
Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultane-
ously converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and
so on. The pair of channels selected may be two single-ended channels or two differential pairs. The
logic states of these pins need to be set up prior to the acquisition time and subsequent falling edge
of CS to correctly set up the multiplexer for that conversion. For further details, see Table 53 (Analog
CS
I
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the internal ADC and framing the serial data transfer. When connecting CS to a processor signal that is
three-stated during reset and/or hibernate, adding a pull-up resistor may prove useful to avoid random
ADC operation.
ADSCLK
I
Serial Clock. Logic input. A serial clock input provides the ADSCLK for accessing the data from the
internal ADC. This clock is also used as the clock source for the conversion process.
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