參數(shù)資料
型號: ADSP-21992BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 31/60頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 176LQFP
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: SPI,SSP
時鐘速率: 160MHz
非易失內(nèi)存: 外部
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 2.50V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 176-LQFP
供應(yīng)商設(shè)備封裝: 176-LQFP(24x24)
包裝: 托盤
ADSP-21992
Rev. A
|
Page 37 of 60
|
August 2007
External Port Read Cycle Timing
Table 21 and Figure 11 describe external port read operations.
For additional information on the ACK signal, see the discus-
Table 21. External Port Read Cycle Timing
Parameter1, 2
Min
Max
Unit
Timing Requirements
tAKW
ACK Strobe Pulse Width
tHCLK
ns
tRDA
RD Asserted to Data Access Setup
tEMICLK – 5+W
3
ns
tADA
Address Valid to Data Access Setup
tEMICLK + W
3
ns
tSDA
Chip Select Asserted to Data Access Setup
tEMICLK + W
3
ns
tSD
Data Valid to RD Deasserted Setup
5
ns
tHRD
RD Deasserted to Data Invalid Hold
0
ns
tDRSAK
ACK Delay from XMS Low
0.5tEMICLK – 1
ns
Switching Characteristics
tCSRS
Chip Select Asserted to RD Asserted Delay
0.5tEMICLK – 3
ns
tARS
Address Valid to RD Setup and Delay
0.5tEMICLK – 3
ns
tRSCS
RD Deasserted to Chip Select Deasserted Setup
0.5tEMICLK – 2
ns
tRW
RD Strobe Pulse Width
tEMICLK–2 + W
3
ns
tRSA
RD Deasserted to Address Invalid Setup
0.5tHCLK – 2
ns
tRWR
RD Deasserted to WR, RD Asserted
tHCLK
ns
1 tEMICLK is the external memory Interface clock period. tHCLK is the peripheral clock period.
2 These are timing parameters that are based on worst-case operating conditions.
3 W = (number of wait states specified in wait register)
tEMICLK.
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