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參數(shù)資料
| 型號： | ADSP-2191MKSTZ-160 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-bit Fixed-Point DSP, 160 MIPS, 160K bytes RAM; Package: 144 ld LQFP (20x20mm); No of Pins: 144; Temperature Range: Comm. |
| 中文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大?。?/td> | 1789K |
| 代理商： | ADSP-2191MKSTZ-160 |
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–33–
REV. A
ADSP-2191M
Serial Ports
Frame Sync operations.
Table 19. Serial Ports1, 2
Parameter
Min
Max
Unit
External Clock Timing Requirements
t
SFSE
TFS/RFS Setup Before TCLK/RCLK3
4ns
t
HFSE
TFS/RFS Hold After TCLK/RCLK3
4ns
t
SDRE
Receive Data Setup Before RCLK3
1.5
ns
t
HDRE
Receive Data Hold After RCLK3
4ns
t
SCLKW
TCLK/RCLK Width
0.5t
HCLK –1
ns
t
SCLK
TCLK/RCLK Period
2t
HCLK
ns
Internal Clock Timing Requirements
t
SFSI
TFS Setup Before TCLK4; RFS Setup Before RCLK3
4ns
t
HFSI
TFS/RFS Hold After TCLK/RCLK3
3ns
t
SDRI
Receive Data Setup Before RCLK3
2ns
t
HDRI
Receive Data Hold After RCLK
3
5ns
External or Internal Clock Switching Characteristics
t
DFSE
TFS/RFS Delay After TCLK/RCLK (Internally
Generated FS)4
14
ns
t
HOFSE
TFS/RFS Hold After TCLK/RCLK (Internally
Generated FS)
4
3ns
External Clock Switching Characteristics
t
DDTE
Transmit Data Delay After TCLK
4
13.4
ns
t
HDTE
Transmit Data Hold After TCLK4
4ns
Internal Clock Switching Characteristics
t
DDTI
Transmit Data Delay After TCLK4
13.4
ns
t
HDTI
Transmit Data Hold After TCLK4
4ns
t
SCLKIW
TCLK/RCLK Width
0.5t
HCLK –3.5
0.5t
HCLK +2.5
ns
Enable and Three-State5 Switching Characteristics
t
DTENE
Data Enable from External TCLK
4
012.1
ns
t
DDTTE
Data Disable from External TCLK
4
13
ns
t
DTENI
Data Enable from Internal TCLK
4
013
ns
t
DDTTI
Data Disable from External TCLK4
12
ns
External Late Frame Sync Switching Characteristics
t
DDTLFSE
Data Delay from Late External TFS with MCE = 1, MFD = 06, 7
10.5
ns
t
DTENLFSE
Data Enable from Late FS or MCE = 1, MFD = 06, 7
3.5
ns
1To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay
and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
2Word selected timing for I2S mode is the same as TFS/RFS timing (normal framing only).
3Referenced to sample edge.
4Referenced to drive edge.
5Only applies to SPORT0/1.
6MCE=1, TFS enable, and TFS valid follow t
DDTENFS and tDDTLFSE.
7If external RFSD/TFS setup to RCLK/TCLK>0.5t
LSCK, tDDTLSCK and tDTENLSCK apply; otherwise tDDTLFSE and tDTENLFS apply.
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