參數(shù)資料
型號： ADSP-2187LKST-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 26.3 MHz, OTHER DSP, PQFP100
封裝： MS-026BED, LQFP-100
文件頁數(shù)： 10/32頁
文件大?。?/td> 223K
代理商： ADSP-2187LKST-160
REV. 0
ADSP-2187L
–10–
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 7. The byte memory space consists of 256 pages,
each of which is 16K
×
8.
The byte memory space on the ADSP-2187L supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg
×
8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
BDMA CONTROL
9
8
BMPAGE
BDMA
OVERLAY
BITS
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
15 14 13 12 11 10
7
6
5
4
3
2
1
0
DM (0
3
3FE3)
Figure 7. BDMA Control Register
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table VI shows the data formats sup-
ported by the BDMA circuit.
Table VI. Data Formats
Internal
Memory Space
BTYPE
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
8
Full Word
Full Word
MSBs
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external
byte memory space. The 8-bit BMPAGE register specifies the
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally the 14-
bit BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
I/O Space (Full Memory Mode)
The ADSP-2187L supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are un-
defined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table V.
Table V. Wait States
Address Range
Wait State Register
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
Composite Memory Select (
CMS
)
The ADSP-2187L has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The
CMS
signal is generated
to have the same timing as each of the individual memory select
signals (
PMS
,
DMS
,
BMS
,
IOMS
) but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the
CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the
PMS
and
DMS
bits in the
CMSSEL register and use the
CMS
pin to drive the chip select
of the memory; use either
DMS
or
PMS
as the additional
address bit.
The
CMS
pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the
CMS
signal at the same time as the
selected memory select signal. All enable bits default to 1 at re-
set, except the
BMS
bit.
Boot Memory Select (
BMS
) Disable
The ADSP-2187L also lets you boot the processor from one ex-
ternal memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the
CMS
to select the first external memory space for
BDMA transfers and
BMS
to select the second external
memory space for booting. The
BMS
signal can be disabled by
setting Bit 3 of the System Control Register to 1. The System
Control Register is illustrated in Figure 6.
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
15 14
13 12 11
10
9
8
7
6
5
4
3
2
1
0
DM (0
3
3FFF)
SYSTEM CONTROL REGISTER
1 = ENABLSPORT0 ENABLE
SPORT1 ENABLE
1 = ENABLED, 0 = DISABLED
SP1 = SERIAL PORT
0 = F1, FO,
IRQ0
,
IRQ1
, SCLK
PWAIT
BMS
ENABLE
0 = ENABLED, 1 = DISABLED
Figure 6. System Control Register
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